1/*************************************************************************************** 2* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2025 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import io.circe.generic.extras.Configuration 20import io.circe.generic.extras.auto._ 21 22import org.chipsalliance.cde.config.Parameters 23import system.SoCParamsKey 24import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry} 25import xiangshan.XSTileKey 26import freechips.rocketchip.devices.debug.DebugModuleKey 27import freechips.rocketchip.diplomacy.AddressSet 28import freechips.rocketchip.util.AsyncQueueParams 29 30case class YamlConfig( 31 PmemRanges: Option[List[MemoryRange]], 32 PMAConfigs: Option[List[PMAConfigEntry]], 33 EnableCHIAsyncBridge: Option[Boolean], 34 L2CacheConfig: Option[L2CacheConfig], 35 L3CacheConfig: Option[L3CacheConfig], 36 DebugModuleBaseAddr: Option[BigInt], 37 WFIResume: Option[Boolean], 38 SeperateDM: Option[Boolean], 39 SeperateTLBus: Option[Boolean], 40 SeperateTLBusRanges: Option[List[AddressSet]] 41) 42 43object YamlParser { 44 implicit val customParserConfig: Configuration = Configuration.default.withDefaults 45 def parseYaml(config: Parameters, yamlFile: String): Parameters = { 46 val yaml = scala.io.Source.fromFile(yamlFile).mkString 47 val json = io.circe.yaml.parser.parse(yaml) match { 48 case Left(value) => throw value 49 case Right(value) => value 50 } 51 val yamlConfig = json.as[YamlConfig] match { 52 case Left(value) => throw value 53 case Right(value) => value 54 } 55 var newConfig = config 56 yamlConfig.PmemRanges.foreach { ranges => 57 newConfig = newConfig.alter((site, here, up) => { 58 case SoCParamsKey => up(SoCParamsKey).copy(PmemRanges = ranges) 59 }) 60 } 61 yamlConfig.PMAConfigs.foreach { pmaConfigs => 62 newConfig = newConfig.alter((site, here, up) => { 63 case SoCParamsKey => up(SoCParamsKey).copy(PMAConfigs = pmaConfigs) 64 }) 65 } 66 yamlConfig.EnableCHIAsyncBridge.foreach { enable => 67 newConfig = newConfig.alter((site, here, up) => { 68 case SoCParamsKey => up(SoCParamsKey).copy( 69 EnableCHIAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 16, sync = 3, safe = false)) 70 ) 71 }) 72 } 73 yamlConfig.L2CacheConfig.foreach(l2 => newConfig = newConfig.alter(l2)) 74 yamlConfig.L3CacheConfig.foreach(l3 => newConfig = newConfig.alter(l3)) 75 yamlConfig.DebugModuleBaseAddr.foreach { addr => 76 newConfig = newConfig.alter((site, here, up) => { 77 case DebugModuleKey => up(DebugModuleKey).map(_.copy(baseAddress = addr)) 78 }) 79 } 80 yamlConfig.WFIResume.foreach { enable => 81 newConfig = newConfig.alter((site, here, up) => { 82 case XSTileKey => up(XSTileKey).map(_.copy(wfiResume = enable)) 83 }) 84 } 85 yamlConfig.SeperateDM.foreach { enable => 86 newConfig = newConfig.alter((site, here, up) => { 87 case SoCParamsKey => up(SoCParamsKey).copy(SeperateDM = enable) 88 }) 89 } 90 yamlConfig.SeperateTLBus.foreach { enable => 91 newConfig = newConfig.alter((site, here, up) => { 92 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBus = enable) 93 }) 94 } 95 yamlConfig.SeperateTLBusRanges.foreach { ranges => 96 newConfig = newConfig.alter((site, here, up) => { 97 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBusRanges = ranges) 98 }) 99 } 100 newConfig 101 } 102} 103