1/*************************************************************************************** 2* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2025 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import io.circe.generic.extras.Configuration 20import io.circe.generic.extras.auto._ 21 22import aia.IMSICParams 23import org.chipsalliance.cde.config.Parameters 24import system.SoCParamsKey 25import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry} 26import xiangshan.XSTileKey 27import freechips.rocketchip.devices.debug.{DebugAttachParams, ExportDebug} 28import freechips.rocketchip.devices.debug.{DMI, JTAG, CJTAG, APB} 29import freechips.rocketchip.devices.debug.{DebugModuleKey, DebugModuleParams} 30import freechips.rocketchip.diplomacy.AddressSet 31import freechips.rocketchip.tile.MaxHartIdBits 32import freechips.rocketchip.util.AsyncQueueParams 33import device.IMSICBusType 34 35case class YamlConfig( 36 Config: Option[String], 37 PmemRanges: Option[List[MemoryRange]], 38 PMAConfigs: Option[List[PMAConfigEntry]], 39 EnableCHIAsyncBridge: Option[Boolean], 40 L2CacheConfig: Option[L2CacheConfig], 41 L3CacheConfig: Option[L3CacheConfig], 42 HartIDBits: Option[Int], 43 DebugAttachProtocals: Option[List[String]], 44 DebugModuleParams: Option[DebugModuleParams], 45 WFIResume: Option[Boolean], 46 SeperateDM: Option[Boolean], 47 SeperateTLBus: Option[Boolean], 48 SeperateTLBusRanges: Option[List[AddressSet]], 49 EnableSeperateTLBusAsyncBridge: Option[Boolean], 50 IMSICBusType: Option[String], 51 IMSICParams: Option[IMSICParams], 52 CHIIssue: Option[String], 53 WFIClockGate: Option[Boolean], 54 EnablePowerDown: Option[Boolean], 55 XSTopPrefix: Option[String], 56 EnableDFX: Option[Boolean], 57 EnableSramCtl: Option[Boolean], 58 EnableCHINS: Option[Boolean], 59) 60 61object YamlParser { 62 implicit val customParserConfig: Configuration = Configuration.default.withDefaults 63 def parseYaml(config: Parameters, yamlFile: String): Parameters = { 64 val yaml = scala.io.Source.fromFile(yamlFile).mkString 65 val json = io.circe.yaml.parser.parse(yaml) match { 66 case Left(value) => throw value 67 case Right(value) => value 68 } 69 val yamlConfig = json.as[YamlConfig] match { 70 case Left(value) => throw value 71 case Right(value) => value 72 } 73 var newConfig = config 74 yamlConfig.Config.foreach { config => 75 newConfig = ArgParser.getConfigByName(config) 76 } 77 yamlConfig.PmemRanges.foreach { ranges => 78 newConfig = newConfig.alter((site, here, up) => { 79 case SoCParamsKey => up(SoCParamsKey).copy(PmemRanges = ranges) 80 }) 81 } 82 yamlConfig.PMAConfigs.foreach { pmaConfigs => 83 newConfig = newConfig.alter((site, here, up) => { 84 case SoCParamsKey => up(SoCParamsKey).copy(PMAConfigs = pmaConfigs) 85 }) 86 } 87 yamlConfig.EnableCHIAsyncBridge.foreach { enable => 88 newConfig = newConfig.alter((site, here, up) => { 89 case SoCParamsKey => up(SoCParamsKey).copy( 90 EnableCHIAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 16, sync = 3, safe = false)) 91 ) 92 }) 93 } 94 yamlConfig.L2CacheConfig.foreach(l2 => newConfig = newConfig.alter(l2)) 95 yamlConfig.L3CacheConfig.foreach(l3 => newConfig = newConfig.alter(l3)) 96 yamlConfig.DebugAttachProtocals.foreach { protocols => 97 newConfig = newConfig.alter((site, here, up) => { 98 case ExportDebug => DebugAttachParams(protocols = protocols.map { 99 case "DMI" => DMI 100 case "JTAG" => JTAG 101 case "CJTAG" => CJTAG 102 case "APB" => APB 103 }.toSet) 104 }) 105 } 106 yamlConfig.HartIDBits.foreach { bits => 107 newConfig = newConfig.alter((site, here, up) => { 108 case MaxHartIdBits => bits 109 }) 110 } 111 yamlConfig.DebugModuleParams.foreach { params => 112 newConfig = newConfig.alter((site, here, up) => { 113 case DebugModuleKey => Some(params) 114 }) 115 } 116 yamlConfig.WFIResume.foreach { enable => 117 newConfig = newConfig.alter((site, here, up) => { 118 case XSTileKey => up(XSTileKey).map(_.copy(wfiResume = enable)) 119 }) 120 } 121 yamlConfig.SeperateDM.foreach { enable => 122 newConfig = newConfig.alter((site, here, up) => { 123 case SoCParamsKey => up(SoCParamsKey).copy(SeperateDM = enable) 124 }) 125 } 126 yamlConfig.SeperateTLBus.foreach { enable => 127 newConfig = newConfig.alter((site, here, up) => { 128 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBus = enable) 129 }) 130 } 131 yamlConfig.SeperateTLBusRanges.foreach { ranges => 132 newConfig = newConfig.alter((site, here, up) => { 133 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBusRanges = ranges) 134 }) 135 } 136 yamlConfig.EnableSeperateTLBusAsyncBridge.foreach { enable => 137 newConfig = newConfig.alter((site, here, up) => { 138 case SoCParamsKey => up(SoCParamsKey).copy( 139 SeperateTLAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 1, sync = 3, safe = false)) 140 ) 141 }) 142 } 143 yamlConfig.IMSICBusType.foreach { busType => 144 newConfig = newConfig.alter((site, here, up) => { 145 case SoCParamsKey => up(SoCParamsKey).copy(IMSICBusType = device.IMSICBusType.withName(busType)) 146 }) 147 } 148 yamlConfig.IMSICParams.foreach { params => 149 newConfig = newConfig.alter((site, here, up) => { 150 case SoCParamsKey => up(SoCParamsKey).copy(IMSICParams = params) 151 }) 152 } 153 yamlConfig.CHIIssue.foreach { issue => 154 newConfig = newConfig.alter((site, here, up) => { 155 case coupledL2.tl2chi.CHIIssue => issue 156 }) 157 } 158 yamlConfig.WFIClockGate.foreach { enable => 159 newConfig = newConfig.alter((site, here, up) => { 160 case SoCParamsKey => up(SoCParamsKey).copy(WFIClockGate = enable) 161 }) 162 } 163 yamlConfig.EnablePowerDown.foreach { enable => 164 newConfig = newConfig.alter((site, here, up) => { 165 case SoCParamsKey => up(SoCParamsKey).copy(EnablePowerDown = enable) 166 }) 167 } 168 yamlConfig.XSTopPrefix.foreach { prefix => 169 newConfig = newConfig.alter((site, here, up) => { 170 case SoCParamsKey => up(SoCParamsKey).copy(XSTopPrefix = Option.when(prefix.nonEmpty)(prefix)) 171 }) 172 } 173 yamlConfig.EnableDFX.foreach { enable => 174 newConfig = newConfig.alter((site, here, up) => { 175 case XSTileKey => up(XSTileKey).map(_.copy(hasMbist = enable)) 176 }) 177 } 178 yamlConfig.EnableSramCtl.foreach { enable => 179 newConfig = newConfig.alter((site, here, up) => { 180 case XSTileKey => up(XSTileKey).map(_.copy(hasSramCtl = enable)) 181 }) 182 } 183 yamlConfig.EnableCHINS.foreach { enable => 184 newConfig = newConfig.alter((site, here, up) => { 185 case coupledL2.tl2chi.NonSecureKey => enable 186 }) 187 } 188 newConfig 189 } 190} 191