xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision e1d5ffc2d93873b72146e78c8f6a904926de8590) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
34
35class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
36{
37  override lazy val desiredName: String = "XSTop"
38
39  ResourceBinding {
40    val width = ResourceInt(2)
41    val model = "freechips,rocketchip-unknown"
42    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
43    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
44    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
45    Resource(ResourceAnchors.root, "width").bind(width)
46    Resource(ResourceAnchors.soc, "width").bind(width)
47    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
48    def bindManagers(xbar: TLNexusNode) = {
49      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
50        manager.resources.foreach(r => r.bind(manager.toResource))
51      }
52    }
53  }
54
55  require(enableCHI)
56
57  // xstile
58  val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
59    case XSCoreParamsKey => tiles.head
60    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
61  })))
62
63  // imsic bus top
64  val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL))
65
66  // interrupts
67  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
68  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
69  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
70  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
71  core_with_l2.clintIntNode := clintIntNode
72  core_with_l2.debugIntNode := debugIntNode
73  core_with_l2.plicIntNode :*= plicIntNode
74  beuIntNode := IntBuffer(2) := core_with_l2.tile.beu_int_source
75  val clint = InModuleBody(clintIntNode.makeIOs())
76  val debug = InModuleBody(debugIntNode.makeIOs())
77  val plic = InModuleBody(plicIntNode.makeIOs())
78  val beu = InModuleBody(beuIntNode.makeIOs())
79
80  // reset nodes
81  val core_rst_node = BundleBridgeSource(() => Reset())
82  core_with_l2.tile.core_reset_sink := core_rst_node
83
84  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
85    FileRegisters.add("dts", dts)
86    FileRegisters.add("graphml", graphML)
87    FileRegisters.add("json", json)
88    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
89
90    val clock = IO(Input(Clock()))
91    val reset = IO(Input(AsyncReset()))
92    val noc_clock = IO(Input(Clock()))
93    val noc_reset = IO(Input(AsyncReset()))
94    val soc_clock = IO(Input(Clock()))
95    val soc_reset = IO(Input(AsyncReset()))
96    val io = IO(new Bundle {
97      val hartId = Input(UInt(p(MaxHartIdBits).W))
98      val riscv_halt = Output(Bool())
99      val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
100      val chi = new PortIO
101      val nodeID = Input(UInt(soc.NodeIDWidthList(issue).W))
102      val clintTime = Input(ValidIO(UInt(64.W)))
103    })
104    // imsic axi4lite io
105    val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x)))
106    val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x)))
107    // imsic tl io
108    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
109    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
110
111    val reset_sync = withClockAndReset(clock, reset) { ResetGen() }
112    val noc_reset_sync = withClockAndReset(noc_clock, noc_reset) { ResetGen() }
113    val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
114
115    // override LazyRawModuleImp's clock and reset
116    childClock := clock
117    childReset := reset_sync
118
119    // device clock and reset
120    wrapper.u_imsic_bus_top.module.clock := soc_clock
121    wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
122
123    // imsic axi4lite io connection
124    wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get)
125    wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get)
126
127    // imsic tl io connection
128    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
129    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
130
131    // input
132    dontTouch(io)
133
134    core_with_l2.module.io.hartId := io.hartId
135    core_with_l2.module.io.nodeID.get := io.nodeID
136    io.riscv_halt := core_with_l2.module.io.cpu_halt
137    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
138
139    EnableClintAsyncBridge match {
140      case Some(param) =>
141        val source = withClockAndReset(soc_clock, soc_reset_sync) {
142          Module(new AsyncQueueSource(UInt(64.W), param))
143        }
144        source.io.enq.valid := io.clintTime.valid
145        source.io.enq.bits := io.clintTime.bits
146        core_with_l2.module.io.clintTime.get <> source.io.async
147      case None =>
148        core_with_l2.module.io.clintTime.get <> io.clintTime
149    }
150
151    EnableCHIAsyncBridge match {
152      case Some(param) =>
153        val sink = withClockAndReset(noc_clock, noc_reset_sync) {
154          Module(new CHIAsyncBridgeSink(param))
155        }
156        sink.io.async <> core_with_l2.module.io.chi.get
157        io.chi <> sink.io.deq
158      case None =>
159        io.chi <> core_with_l2.module.io.chi.get
160    }
161
162    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
163    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
164    // tie off core soft reset
165    core_rst_node.out.head._1 := false.B.asAsyncReset
166
167    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
168
169    withClockAndReset(clock, reset_sync) {
170      // Modules are reset one by one
171      // reset ----> SYNC --> Core
172      val resetChain = Seq(Seq(core_with_l2.module))
173      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
174    }
175
176  }
177
178  lazy val module = new XSNoCTopImp(this)
179}
180