xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision 8a020714df826c6ac860308700137855ecd6ba07) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
34
35class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
36{
37  override lazy val desiredName: String = "XSTop"
38
39  ResourceBinding {
40    val width = ResourceInt(2)
41    val model = "freechips,rocketchip-unknown"
42    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
43    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
44    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
45    Resource(ResourceAnchors.root, "width").bind(width)
46    Resource(ResourceAnchors.soc, "width").bind(width)
47    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
48    def bindManagers(xbar: TLNexusNode) = {
49      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
50        manager.resources.foreach(r => r.bind(manager.toResource))
51      }
52    }
53  }
54
55  // xstile
56  val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
57    case XSCoreParamsKey => tiles.head
58    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
59  })))
60
61  // imsic bus top
62  val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL))
63
64  // interrupts
65  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
66  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
67  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
68  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
69  core_with_l2.clintIntNode := clintIntNode
70  core_with_l2.debugIntNode := debugIntNode
71  core_with_l2.plicIntNode :*= plicIntNode
72  beuIntNode := IntBuffer(2) := core_with_l2.tile.beu_int_source
73  val clint = InModuleBody(clintIntNode.makeIOs())
74  val debug = InModuleBody(debugIntNode.makeIOs())
75  val plic = InModuleBody(plicIntNode.makeIOs())
76  val beu = InModuleBody(beuIntNode.makeIOs())
77
78  // reset nodes
79  val core_rst_node = BundleBridgeSource(() => Reset())
80  core_with_l2.tile.core_reset_sink := core_rst_node
81
82  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
83    FileRegisters.add("dts", dts)
84    FileRegisters.add("graphml", graphML)
85    FileRegisters.add("json", json)
86    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
87
88    val clock = IO(Input(Clock()))
89    val reset = IO(Input(AsyncReset()))
90    val noc_clock = IO(Input(Clock()))
91    val noc_reset = IO(Input(AsyncReset()))
92    val soc_clock = IO(Input(Clock()))
93    val soc_reset = IO(Input(AsyncReset()))
94    val io = IO(new Bundle {
95      val hartId = Input(UInt(p(MaxHartIdBits).W))
96      val riscv_halt = Output(Bool())
97      val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
98      val chi = new PortIO
99      val nodeID = Input(UInt(soc.NodeIDWidthList(issue).W))
100      val clintTime = Input(ValidIO(UInt(64.W)))
101    })
102    // imsic axi4lite io
103    val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x)))
104    val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x)))
105    // imsic tl io
106    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
107    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
108
109    val reset_sync = withClockAndReset(clock, reset) { ResetGen() }
110    val noc_reset_sync = withClockAndReset(noc_clock, noc_reset) { ResetGen() }
111    val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
112
113    // override LazyRawModuleImp's clock and reset
114    childClock := clock
115    childReset := reset_sync
116
117    // device clock and reset
118    wrapper.u_imsic_bus_top.module.clock := soc_clock
119    wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
120
121    // imsic axi4lite io connection
122    wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get)
123    wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get)
124
125    // imsic tl io connection
126    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
127    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
128
129    // input
130    dontTouch(io)
131
132    core_with_l2.module.io.hartId := io.hartId
133    core_with_l2.module.io.nodeID.get := io.nodeID
134    io.riscv_halt := core_with_l2.module.io.cpu_halt
135    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
136
137    val clintTimeAsyncQueueSource = withClockAndReset(soc_clock, soc_reset_sync) { Module(new AsyncQueueSource(UInt(64.W), AsyncQueueParams(1))) }
138    clintTimeAsyncQueueSource.io.enq.valid := io.clintTime.valid
139    clintTimeAsyncQueueSource.io.enq.bits := io.clintTime.bits
140    core_with_l2.module.io.clintTimeAsync <> clintTimeAsyncQueueSource.io.async
141
142    val chiAsyncBridgeSink = withClockAndReset(noc_clock, noc_reset_sync) {
143      Module(new CHIAsyncBridgeSink(soc.CHIAsyncBridge))
144    }
145    chiAsyncBridgeSink.io.async <> core_with_l2.module.io.chi.get
146    io.chi <> chiAsyncBridgeSink.io.deq
147
148    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
149    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
150    // tie off core soft reset
151    core_rst_node.out.head._1 := false.B.asAsyncReset
152
153    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
154
155    withClockAndReset(clock, reset_sync) {
156      // Modules are reset one by one
157      // reset ----> SYNC --> Core
158      val resetChain = Seq(Seq(core_with_l2.module))
159      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
160    }
161
162  }
163
164  lazy val module = new XSNoCTopImp(this)
165}
166