xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision 75ed9f4b75e035c224d8b7cc64c031e797e909ae) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
34import chisel3.experimental.{annotate, ChiselAnnotation}
35import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
36
37class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
38{
39  override lazy val desiredName: String = "XSTop"
40
41  ResourceBinding {
42    val width = ResourceInt(2)
43    val model = "freechips,rocketchip-unknown"
44    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
45    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
46    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
47    Resource(ResourceAnchors.root, "width").bind(width)
48    Resource(ResourceAnchors.soc, "width").bind(width)
49    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
50    def bindManagers(xbar: TLNexusNode) = {
51      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
52        manager.resources.foreach(r => r.bind(manager.toResource))
53      }
54    }
55  }
56
57  require(enableCHI)
58
59  // xstile
60  val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
61    case XSCoreParamsKey => tiles.head
62    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
63  })))
64
65  // imsic bus top
66  val u_imsic_bus_top = LazyModule(new imsic_bus_top(
67    useTL = soc.IMSICUseTL,
68    baseAddress = (0x3A800000, 0x3B000000)
69  ))
70
71  // interrupts
72  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
73  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
74  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
75  val nmiIntNode = IntSourceNode(IntSourcePortSimple(1, 1, (new NonmaskableInterruptIO).elements.size))
76  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
77  core_with_l2.clintIntNode := clintIntNode
78  core_with_l2.debugIntNode := debugIntNode
79  core_with_l2.plicIntNode :*= plicIntNode
80  core_with_l2.nmiIntNode := nmiIntNode
81  beuIntNode := core_with_l2.beuIntNode
82  val clint = InModuleBody(clintIntNode.makeIOs())
83  val debug = InModuleBody(debugIntNode.makeIOs())
84  val plic = InModuleBody(plicIntNode.makeIOs())
85  val nmi = InModuleBody(nmiIntNode.makeIOs())
86  val beu = InModuleBody(beuIntNode.makeIOs())
87
88  // reset nodes
89  val core_rst_node = BundleBridgeSource(() => Reset())
90  core_with_l2.tile.core_reset_sink := core_rst_node
91
92  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
93    soc.XSTopPrefix.foreach { prefix =>
94      val mod = this.toNamed
95      annotate(new ChiselAnnotation {
96        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
97      })
98    }
99    FileRegisters.add("dts", dts)
100    FileRegisters.add("graphml", graphML)
101    FileRegisters.add("json", json)
102    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
103
104    val clock = IO(Input(Clock()))
105    val reset = IO(Input(AsyncReset()))
106    val noc_clock = EnableCHIAsyncBridge.map(_ => IO(Input(Clock())))
107    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
108    val soc_clock = IO(Input(Clock()))
109    val soc_reset = IO(Input(AsyncReset()))
110    val io = IO(new Bundle {
111      val hartId = Input(UInt(p(MaxHartIdBits).W))
112      val riscv_halt = Output(Bool())
113      val riscv_critical_error = Output(Bool())
114      val hartIsInReset = Output(Bool())
115      val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
116      val chi = new PortIO
117      val nodeID = Input(UInt(soc.NodeIDWidthList(issue).W))
118      val clintTime = Input(ValidIO(UInt(64.W)))
119      val traceCoreInterface = new Bundle {
120        val fromEncoder = Input(new Bundle {
121          val enable = Bool()
122          val stall  = Bool()
123        })
124        val toEncoder   = Output(new Bundle {
125          val cause     = UInt(TraceCauseWidth.W)
126          val tval      = UInt(TraceTvalWidth.W)
127          val priv      = UInt(TracePrivWidth.W)
128          val iaddr     = UInt((TraceTraceGroupNum * TraceIaddrWidth).W)
129          val itype     = UInt((TraceTraceGroupNum * TraceItypeWidth).W)
130          val iretire   = UInt((TraceTraceGroupNum * TraceIretireWidthCompressed).W)
131          val ilastsize = UInt((TraceTraceGroupNum * TraceIlastsizeWidth).W)
132        })
133      }
134    })
135    // imsic axi4lite io
136    val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
137    // imsic tl io
138    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
139    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
140
141    val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen() })
142    val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
143
144    // device clock and reset
145    wrapper.u_imsic_bus_top.module.clock := soc_clock
146    wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
147
148    // imsic axi4lite io connection
149    wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
150
151    // imsic tl io connection
152    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
153    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
154
155    // input
156    dontTouch(io)
157
158    core_with_l2.module.clock := clock
159    core_with_l2.module.reset := reset
160    core_with_l2.module.noc_reset.foreach(_ := noc_reset.get)
161    core_with_l2.module.soc_reset := soc_reset
162    core_with_l2.module.io.hartId := io.hartId
163    core_with_l2.module.io.nodeID.get := io.nodeID
164    io.riscv_halt := core_with_l2.module.io.cpu_halt
165    io.riscv_critical_error := core_with_l2.module.io.cpu_crtical_error
166    io.hartIsInReset := core_with_l2.module.io.hartIsInReset
167    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
168    // trace Interface
169    val traceInterface = core_with_l2.module.io.traceCoreInterface
170    traceInterface.fromEncoder := io.traceCoreInterface.fromEncoder
171    io.traceCoreInterface.toEncoder.priv := traceInterface.toEncoder.priv
172    io.traceCoreInterface.toEncoder.cause := traceInterface.toEncoder.trap.cause
173    io.traceCoreInterface.toEncoder.tval := traceInterface.toEncoder.trap.tval
174    io.traceCoreInterface.toEncoder.iaddr := VecInit(traceInterface.toEncoder.groups.map(_.bits.iaddr)).asUInt
175    io.traceCoreInterface.toEncoder.itype := VecInit(traceInterface.toEncoder.groups.map(_.bits.itype)).asUInt
176    io.traceCoreInterface.toEncoder.iretire := VecInit(traceInterface.toEncoder.groups.map(_.bits.iretire)).asUInt
177    io.traceCoreInterface.toEncoder.ilastsize := VecInit(traceInterface.toEncoder.groups.map(_.bits.ilastsize)).asUInt
178
179    EnableClintAsyncBridge match {
180      case Some(param) =>
181        withClockAndReset(soc_clock, soc_reset_sync) {
182          val source = Module(new AsyncQueueSource(UInt(64.W), param))
183          source.io.enq.valid := io.clintTime.valid
184          source.io.enq.bits := io.clintTime.bits
185          core_with_l2.module.io.clintTime <> source.io.async
186        }
187      case None =>
188        core_with_l2.module.io.clintTime <> io.clintTime
189    }
190
191    EnableCHIAsyncBridge match {
192      case Some(param) =>
193        withClockAndReset(noc_clock.get, noc_reset_sync.get) {
194          val sink = Module(new CHIAsyncBridgeSink(param))
195          sink.io.async <> core_with_l2.module.io.chi
196          io.chi <> sink.io.deq
197        }
198      case None =>
199        io.chi <> core_with_l2.module.io.chi
200    }
201
202    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
203    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
204    // tie off core soft reset
205    core_rst_node.out.head._1 := false.B.asAsyncReset
206
207    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
208  }
209
210  lazy val module = new XSNoCTopImp(this)
211}
212