xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision 3ea4388c307775f866cbebd6405f8201d60f1e53) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.PortIO
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueue, AsyncQueueParams}
34
35class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
36{
37  override lazy val desiredName: String = "XSTop"
38
39  ResourceBinding {
40    val width = ResourceInt(2)
41    val model = "freechips,rocketchip-unknown"
42    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
43    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
44    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
45    Resource(ResourceAnchors.root, "width").bind(width)
46    Resource(ResourceAnchors.soc, "width").bind(width)
47    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
48    def bindManagers(xbar: TLNexusNode) = {
49      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
50        manager.resources.foreach(r => r.bind(manager.toResource))
51      }
52    }
53  }
54
55  // xstile
56  val core_with_l2 = LazyModule(new XSTile()(p.alter((site, here, up) => {
57    case XSCoreParamsKey => tiles.head
58    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
59  })))
60
61  // imsic bus top
62  val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL))
63
64  // interrupts
65  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
66  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
67  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
68  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
69  core_with_l2.clint_int_node := IntBuffer(2) := clintIntNode
70  core_with_l2.debug_int_node := IntBuffer(2) := debugIntNode
71  core_with_l2.plic_int_node :*= IntBuffer(2) :*= plicIntNode
72  beuIntNode := IntBuffer(2) := core_with_l2.beu_int_source
73  val clint = InModuleBody(clintIntNode.makeIOs())
74  val debug = InModuleBody(debugIntNode.makeIOs())
75  val plic = InModuleBody(plicIntNode.makeIOs())
76  val beu = InModuleBody(beuIntNode.makeIOs())
77
78  // reset nodes
79  val core_rst_node = BundleBridgeSource(() => Reset())
80  core_with_l2.core_reset_sink := core_rst_node
81
82  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
83    FileRegisters.add("dts", dts)
84    FileRegisters.add("graphml", graphML)
85    FileRegisters.add("json", json)
86    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
87
88    val clock = IO(Input(Clock()))
89    val reset = IO(Input(AsyncReset()))
90    val bus_clock = IO(Input(Clock()))
91    val bus_reset = IO(Input(AsyncReset()))
92    val io = IO(new Bundle {
93      val hartId = Input(UInt(p(MaxHartIdBits).W))
94      val riscv_halt = Output(Bool())
95      val riscv_rst_vec = Input(UInt(38.W))
96      val chi = new PortIO
97      val nodeID = Input(UInt(p(SoCParamsKey).NodeIDWidth.W))
98      val clintTime = Input(ValidIO(UInt(64.W)))
99    })
100    // imsic axi4lite io
101    val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x)))
102    val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x)))
103    // imsic tl io
104    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
105    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
106
107    val reset_sync = withClockAndReset(clock, reset) { ResetGen() }
108    val bus_reset_sync = withClockAndReset(bus_clock, bus_reset) { ResetGen() }
109
110    // override LazyRawModuleImp's clock and reset
111    childClock := clock
112    childReset := reset_sync
113
114    // bus clock and reset
115    wrapper.u_imsic_bus_top.module.clock := bus_clock
116    wrapper.u_imsic_bus_top.module.reset := bus_reset_sync
117
118    // imsic axi4lite io connection
119    wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get)
120    wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get)
121
122    // imsic tl io connection
123    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
124    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
125
126    // input
127    dontTouch(io)
128
129    core_with_l2.module.io.hartId := io.hartId
130    core_with_l2.module.io.nodeID.get := io.nodeID
131    core_with_l2.module.io.chi.get <> io.chi
132    io.riscv_halt := core_with_l2.module.io.cpu_halt
133    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
134
135    val clintTimeAsyncQueue = Module(new AsyncQueue(UInt(64.W), AsyncQueueParams(1)))
136    clintTimeAsyncQueue.io.enq_clock := bus_clock
137    clintTimeAsyncQueue.io.enq_reset := bus_reset_sync.asBool
138    clintTimeAsyncQueue.io.deq_clock := clock
139    clintTimeAsyncQueue.io.deq_reset := reset_sync.asBool
140    clintTimeAsyncQueue.io.enq.valid := io.clintTime.valid
141    clintTimeAsyncQueue.io.enq.bits := io.clintTime.bits
142    clintTimeAsyncQueue.io.deq.ready := true.B
143    core_with_l2.module.io.clintTime.valid := clintTimeAsyncQueue.io.deq.valid
144    core_with_l2.module.io.clintTime.bits := clintTimeAsyncQueue.io.deq.bits
145
146    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
147    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
148    // tie off core soft reset
149    core_rst_node.out.head._1 := false.B.asAsyncReset
150
151    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
152
153    withClockAndReset(clock, reset_sync) {
154      // Modules are reset one by one
155      // reset ----> SYNC --> Core
156      val resetChain = Seq(Seq(core_with_l2.module))
157      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
158    }
159
160  }
161
162  lazy val module = new XSNoCTopImp(this)
163}
164