1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import device._ 26import org.chipsalliance.cde.config._ 27import freechips.rocketchip.amba.axi4._ 28import freechips.rocketchip.diplomacy._ 29import freechips.rocketchip.interrupts._ 30import freechips.rocketchip.tilelink._ 31import coupledL2.tl2chi.PortIO 32import freechips.rocketchip.tile.MaxHartIdBits 33 34class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter 35{ 36 override lazy val desiredName: String = "XSTop" 37 38 ResourceBinding { 39 val width = ResourceInt(2) 40 val model = "freechips,rocketchip-unknown" 41 Resource(ResourceAnchors.root, "model").bind(ResourceString(model)) 42 Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev")) 43 Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc")) 44 Resource(ResourceAnchors.root, "width").bind(width) 45 Resource(ResourceAnchors.soc, "width").bind(width) 46 Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1)) 47 def bindManagers(xbar: TLNexusNode) = { 48 ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager => 49 manager.resources.foreach(r => r.bind(manager.toResource)) 50 } 51 } 52 } 53 54 // xstile 55 val core_with_l2 = LazyModule(new XSTile()(p.alter((site, here, up) => { 56 case XSCoreParamsKey => tiles.head 57 case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId) 58 }))) 59 60 // imsic bus top 61 val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL)) 62 63 // interrupts 64 val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2)) 65 val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1)) 66 val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1)) 67 val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1)) 68 core_with_l2.clint_int_node := IntBuffer() := clintIntNode 69 core_with_l2.debug_int_node := IntBuffer() := debugIntNode 70 core_with_l2.plic_int_node :*= IntBuffer() :*= plicIntNode 71 beuIntNode := IntBuffer() := core_with_l2.beu_int_source 72 val clint = InModuleBody(clintIntNode.makeIOs()) 73 val debug = InModuleBody(debugIntNode.makeIOs()) 74 val plic = InModuleBody(plicIntNode.makeIOs()) 75 val beu = InModuleBody(beuIntNode.makeIOs()) 76 77 // reset nodes 78 val core_rst_node = BundleBridgeSource(() => Reset()) 79 core_with_l2.core_reset_sink := core_rst_node 80 81 class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) { 82 FileRegisters.add("dts", dts) 83 FileRegisters.add("graphml", graphML) 84 FileRegisters.add("json", json) 85 FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader()) 86 87 val clock = IO(Input(Clock())) 88 val reset = IO(Input(AsyncReset())) 89 val bus_clock = IO(Input(Clock())) 90 val bus_reset = IO(Input(AsyncReset())) 91 val io = IO(new Bundle { 92 val hartId = Input(UInt(p(MaxHartIdBits).W)) 93 val riscv_halt = Output(Bool()) 94 val riscv_rst_vec = Input(UInt(38.W)) 95 val chi = new PortIO 96 val nodeID = Input(UInt(p(SoCParamsKey).NodeIDWidth.W)) 97 }) 98 // imsic axi4lite io 99 val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x))) 100 val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x))) 101 // imsic tl io 102 val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue))) 103 val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue))) 104 105 val reset_sync = withClockAndReset(clock, reset) { ResetGen() } 106 val bus_reset_sync = withClockAndReset(bus_clock, bus_reset) { ResetGen() } 107 108 // override LazyRawModuleImp's clock and reset 109 childClock := clock 110 childReset := reset_sync 111 112 // bus clock and reset 113 wrapper.u_imsic_bus_top.module.clock := bus_clock 114 wrapper.u_imsic_bus_top.module.reset := bus_reset_sync 115 116 // imsic axi4lite io connection 117 wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get) 118 wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get) 119 120 // imsic tl io connection 121 wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get) 122 wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get) 123 124 // input 125 dontTouch(io) 126 127 core_with_l2.module.io.hartId := io.hartId 128 core_with_l2.module.io.nodeID.get := io.nodeID 129 core_with_l2.module.io.chi.get <> io.chi 130 io.riscv_halt := core_with_l2.module.io.cpu_halt 131 core_with_l2.module.io.reset_vector := io.riscv_rst_vec 132 // tie off core soft reset 133 core_rst_node.out.head._1 := false.B.asAsyncReset 134 135 core_with_l2.module.io.debugTopDown.l3MissMatch := false.B 136 137 withClockAndReset(clock, reset_sync) { 138 // Modules are reset one by one 139 // reset ----> SYNC --> Core 140 val resetChain = Seq(Seq(core_with_l2.module)) 141 ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform) 142 } 143 144 } 145 146 lazy val module = new XSNoCTopImp(this) 147} 148