xref: /XiangShan/src/main/scala/top/Top.scala (revision 4176c33937a5547113be7a0c2411a74f09cc2dfd) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
24import utility._
25import system._
26import device._
27import chisel3.stage.ChiselGeneratorAnnotation
28import org.chipsalliance.cde.config._
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.tilelink._
31import freechips.rocketchip.jtag.JTAGIO
32import chisel3.experimental.{annotate, ChiselAnnotation}
33import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
34
35abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
36  with BindingScope
37{
38  val misc = LazyModule(new SoCMisc())
39  lazy val dts = DTS(bindingTree)
40  lazy val json = JSON(bindingTree)
41}
42
43class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
44{
45  ResourceBinding {
46    val width = ResourceInt(2)
47    val model = "freechips,rocketchip-unknown"
48    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
49    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
50    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
51    Resource(ResourceAnchors.root, "width").bind(width)
52    Resource(ResourceAnchors.soc, "width").bind(width)
53    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
54    def bindManagers(xbar: TLNexusNode) = {
55      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
56        manager.resources.foreach(r => r.bind(manager.toResource))
57      }
58    }
59    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
60    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
61  }
62
63  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
64
65  val core_with_l2 = tiles.map(coreParams =>
66    LazyModule(new XSTile()(p.alterPartial({
67      case XSCoreParamsKey => coreParams
68    })))
69  )
70
71  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
72    LazyModule(new HuanCun()(new Config((_, _, _) => {
73      case HCCacheParamsKey => l3param.copy(
74        hartIds = tiles.map(_.HartId),
75        FPGAPlatform = debugOpts.FPGAPlatform
76      )
77    })))
78  )
79
80  // recieve all prefetch req from cores
81  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
82    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
83  }
84
85  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
86    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
87    case None => None
88  }
89
90  for (i <- 0 until NumCores) {
91    core_with_l2(i).clint_int_node := misc.clint.intnode
92    core_with_l2(i).plic_int_node :*= misc.plic.intnode
93    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
94    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
95    misc.peripheral_ports(i) := core_with_l2(i).uncache
96    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
97    memblock_pf_recv_nodes(i).map(recv => {
98      println(s"Connecting Core_${i}'s L1 pf source to L3!")
99      recv := core_with_l2(i).core_l3_pf_port.get
100    })
101  }
102
103  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
104  l3cacheOpt.map(_.intnode.map(int => {
105    misc.plic.intnode := IntBuffer() := int
106  }))
107
108  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
109    l3cacheOpt.get.rst_nodes.get
110  } else {
111    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
112  }
113
114  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
115    case (source, sink) =>  sink := source
116  })
117
118  l3cacheOpt match {
119    case Some(l3) =>
120      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
121      l3.pf_recv_node.map(recv => {
122        println("Connecting L1 prefetcher to L3!")
123        recv := l3_pf_sender_opt.get
124      })
125      l3.tpmeta_recv_node.foreach(recv => {
126        for ((core, i) <- core_with_l2.zipWithIndex) {
127          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
128          recv := core.core_l3_tpmeta_source_port.get
129        }
130      })
131      l3.tpmeta_send_node.foreach(send => {
132        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
133        broadcast.node := send
134        for ((core, i) <- core_with_l2.zipWithIndex) {
135          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
136          core.core_l3_tpmeta_sink_port.get := broadcast.node
137        }
138      })
139    case None =>
140  }
141
142  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
143    soc.XSTopPrefix.foreach { prefix =>
144      val mod = this.toNamed
145      annotate(new ChiselAnnotation {
146        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
147      })
148    }
149
150    FileRegisters.add("dts", dts)
151    FileRegisters.add("graphml", graphML)
152    FileRegisters.add("json", json)
153    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
154
155    val dma = IO(Flipped(misc.dma.cloneType))
156    val peripheral = IO(misc.peripheral.cloneType)
157    val memory = IO(misc.memory.cloneType)
158
159    misc.dma <> dma
160    peripheral <> misc.peripheral
161    memory <> misc.memory
162
163    val io = IO(new Bundle {
164      val clock = Input(Bool())
165      val reset = Input(AsyncReset())
166      val sram_config = Input(UInt(16.W))
167      val extIntrs = Input(UInt(NrExtIntr.W))
168      val pll0_lock = Input(Bool())
169      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
170      val systemjtag = new Bundle {
171        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
172        val reset = Input(AsyncReset()) // No reset allowed on top
173        val mfr_id = Input(UInt(11.W))
174        val part_number = Input(UInt(16.W))
175        val version = Input(UInt(4.W))
176      }
177      val debug_reset = Output(Bool())
178      val rtc_clock = Input(Bool())
179      val cacheable_check = new TLPMAIO()
180      val riscv_halt = Output(Vec(NumCores, Bool()))
181      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
182    })
183
184    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
185    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
186
187    // override LazyRawModuleImp's clock and reset
188    childClock := io.clock.asClock
189    childReset := reset_sync
190
191    // output
192    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
193
194    // input
195    dontTouch(dma)
196    dontTouch(io)
197    dontTouch(peripheral)
198    dontTouch(memory)
199    misc.module.ext_intrs := io.extIntrs
200    misc.module.rtc_clock := io.rtc_clock
201    misc.module.pll0_lock := io.pll0_lock
202    misc.module.cacheable_check <> io.cacheable_check
203
204    io.pll0_ctrl <> misc.module.pll0_ctrl
205
206    for ((core, i) <- core_with_l2.zipWithIndex) {
207      core.module.io.hartId := i.U
208      io.riscv_halt(i) := core.module.io.cpu_halt
209      core.module.io.reset_vector := io.riscv_rst_vec(i)
210    }
211
212    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
213      // tie off core soft reset
214      for(node <- core_rst_nodes){
215        node.out.head._1 := false.B.asAsyncReset
216      }
217    }
218
219    l3cacheOpt match {
220      case Some(l3) =>
221        l3.pf_recv_node match {
222          case Some(recv) =>
223            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
224            for (i <- 0 until NumCores) {
225              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
226                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
227                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
228              }
229            }
230          case None =>
231        }
232        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
233        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
234      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
235    }
236
237    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
238    misc.module.debug_module_io.clock := io.clock
239    misc.module.debug_module_io.reset := reset_sync
240
241    misc.module.debug_module_io.debugIO.reset := misc.module.reset
242    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
243    // TODO: delay 3 cycles?
244    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
245    // jtag connector
246    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
247      x.jtag        <> io.systemjtag.jtag
248      x.reset       := jtag_reset_sync
249      x.mfr_id      := io.systemjtag.mfr_id
250      x.part_number := io.systemjtag.part_number
251      x.version     := io.systemjtag.version
252    }
253
254    withClockAndReset(io.clock.asClock, reset_sync) {
255      // Modules are reset one by one
256      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
257      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
258      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
259    }
260
261  }
262
263  lazy val module = new XSTopImp(this)
264}
265
266object TopMain extends App {
267  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
268
269  // tools: init to close dpi-c when in fpga
270  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
271  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
272  val enableConstantin = config(DebugOptionsKey).EnableConstantin
273  Constantin.init(enableConstantin && !envInFPGA)
274  ChiselDB.init(enableChiselDB && !envInFPGA)
275
276  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
277  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
278  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
279}
280