1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package top 19 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import system._ 26import org.chipsalliance.cde.config._ 27import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, MaxHartIdBits, XLen} 28import xiangshan.frontend.icache.ICacheParameters 29import freechips.rocketchip.devices.debug._ 30import openLLC.OpenLLCParam 31import freechips.rocketchip.diplomacy._ 32import xiangshan.backend.dispatch.DispatchParameters 33import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 34import xiangshan.cache.DCacheParameters 35import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 36import device.EnableJtag 37import huancun._ 38import coupledL2._ 39import coupledL2.prefetch._ 40 41class BaseConfig(n: Int) extends Config((site, here, up) => { 42 case XLen => 64 43 case DebugOptionsKey => DebugOptions() 44 case SoCParamsKey => SoCParameters() 45 case PMParameKey => PMParameters() 46 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 47 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 48 case DebugModuleKey => Some(DebugModuleParams( 49 nAbstractDataWords = (if (site(XLen) == 32) 1 else if (site(XLen) == 64) 2 else 4), 50 maxSupportedSBAccess = site(XLen), 51 hasBusMaster = true, 52 baseAddress = BigInt(0x38020000), 53 nScratch = 2, 54 crossingHasSafeReset = false, 55 hasHartResets = true 56 )) 57 case JtagDTMKey => JtagDTMKey 58 case MaxHartIdBits => log2Up(n) max 6 59 case EnableJtag => true.B 60}) 61 62// Synthesizable minimal XiangShan 63// * It is still an out-of-order, super-scalaer arch 64// * L1 cache included 65// * L2 cache NOT included 66// * L3 cache included 67class MinimalConfig(n: Int = 1) extends Config( 68 new BaseConfig(n).alter((site, here, up) => { 69 case XSTileKey => up(XSTileKey).map( 70 p => p.copy( 71 DecodeWidth = 6, 72 RenameWidth = 6, 73 RobCommitWidth = 8, 74 FetchWidth = 4, 75 VirtualLoadQueueSize = 24, 76 LoadQueueRARSize = 24, 77 LoadQueueRAWSize = 12, 78 LoadQueueReplaySize = 24, 79 LoadUncacheBufferSize = 8, 80 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 81 RollbackGroupSize = 8, 82 StoreQueueSize = 20, 83 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 84 StoreQueueForwardWithMask = true, 85 // ============ VLSU ============ 86 VlMergeBufferSize = 16, 87 VsMergeBufferSize = 8, 88 UopWritebackWidth = 2, 89 // ============================== 90 RobSize = 48, 91 RabSize = 96, 92 FtqSize = 8, 93 IBufSize = 24, 94 IBufNBank = 6, 95 StoreBufferSize = 4, 96 StoreBufferThreshold = 3, 97 IssueQueueSize = 10, 98 IssueQueueCompEntrySize = 4, 99 dpParams = DispatchParameters( 100 IntDqSize = 12, 101 FpDqSize = 12, 102 LsDqSize = 12, 103 IntDqDeqWidth = 8, 104 FpDqDeqWidth = 6, 105 VecDqDeqWidth = 6, 106 LsDqDeqWidth = 6 107 ), 108 intPreg = IntPregParams( 109 numEntries = 64, 110 numRead = None, 111 numWrite = None, 112 ), 113 vfPreg = VfPregParams( 114 numEntries = 160, 115 numRead = None, 116 numWrite = None, 117 ), 118 icacheParameters = ICacheParameters( 119 nSets = 64, // 16KB ICache 120 tagECC = Some("parity"), 121 dataECC = Some("parity"), 122 replacer = Some("setplru"), 123 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)), 124 ), 125 dcacheParametersOpt = Some(DCacheParameters( 126 nSets = 64, // 32KB DCache 127 nWays = 8, 128 tagECC = Some("secded"), 129 dataECC = Some("secded"), 130 replacer = Some("setplru"), 131 nMissEntries = 4, 132 nProbeEntries = 4, 133 nReleaseEntries = 8, 134 nMaxPrefetchEntry = 2, 135 enableTagEcc = true, 136 enableDataEcc = true, 137 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 138 )), 139 // ============ BPU =============== 140 EnableLoop = false, 141 EnableGHistDiff = false, 142 FtbSize = 256, 143 FtbWays = 2, 144 RasSize = 8, 145 RasSpecSize = 16, 146 TageTableInfos = 147 Seq((512, 4, 6), 148 (512, 9, 6), 149 (1024, 19, 6)), 150 SCNRows = 128, 151 SCNTables = 2, 152 SCHistLens = Seq(0, 5), 153 ITTageTableInfos = 154 Seq((256, 4, 7), 155 (256, 8, 7), 156 (512, 16, 7)), 157 // ================================ 158 itlbParameters = TLBParameters( 159 name = "itlb", 160 fetchi = true, 161 useDmode = false, 162 NWays = 4, 163 ), 164 ldtlbParameters = TLBParameters( 165 name = "ldtlb", 166 NWays = 4, 167 partialStaticPMP = true, 168 outsideRecvFlush = true, 169 outReplace = false, 170 lgMaxSize = 4 171 ), 172 sttlbParameters = TLBParameters( 173 name = "sttlb", 174 NWays = 4, 175 partialStaticPMP = true, 176 outsideRecvFlush = true, 177 outReplace = false, 178 lgMaxSize = 4 179 ), 180 hytlbParameters = TLBParameters( 181 name = "hytlb", 182 NWays = 4, 183 partialStaticPMP = true, 184 outsideRecvFlush = true, 185 outReplace = false, 186 lgMaxSize = 4 187 ), 188 pftlbParameters = TLBParameters( 189 name = "pftlb", 190 NWays = 4, 191 partialStaticPMP = true, 192 outsideRecvFlush = true, 193 outReplace = false, 194 lgMaxSize = 4 195 ), 196 btlbParameters = TLBParameters( 197 name = "btlb", 198 NWays = 4, 199 ), 200 l2tlbParameters = L2TLBParameters( 201 l3Size = 4, 202 l2Size = 4, 203 l1nSets = 4, 204 l1nWays = 4, 205 l1ReservedBits = 1, 206 l0nSets = 4, 207 l0nWays = 8, 208 l0ReservedBits = 0, 209 spSize = 4, 210 ), 211 L2CacheParamsOpt = Some(L2Param( 212 name = "L2", 213 ways = 8, 214 sets = 128, 215 echoField = Seq(huancun.DirtyField()), 216 prefetch = Nil, 217 clientCaches = Seq(L1Param( 218 "dcache", 219 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 220 )), 221 )), 222 L2NBanks = 2, 223 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 224 ) 225 ) 226 case SoCParamsKey => 227 val tiles = site(XSTileKey) 228 up(SoCParamsKey).copy( 229 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 230 sets = 1024, 231 inclusive = false, 232 clientCaches = tiles.map{ core => 233 val clientDirBytes = tiles.map{ t => 234 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 235 }.sum 236 val l2params = core.L2CacheParamsOpt.get.toCacheParams 237 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 238 }, 239 simulation = !site(DebugOptionsKey).FPGAPlatform, 240 prefetch = None 241 )), 242 L3NBanks = 1 243 ) 244 }) 245) 246 247// Non-synthesizable MinimalConfig, for fast simulation only 248class MinimalSimConfig(n: Int = 1) extends Config( 249 new MinimalConfig(n).alter((site, here, up) => { 250 case XSTileKey => up(XSTileKey).map(_.copy( 251 dcacheParametersOpt = None, 252 softPTW = true 253 )) 254 case SoCParamsKey => up(SoCParamsKey).copy( 255 L3CacheParamsOpt = None 256 ) 257 }) 258) 259 260case class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 261 case XSTileKey => 262 val sets = n * 1024 / ways / 64 263 up(XSTileKey).map(_.copy( 264 dcacheParametersOpt = Some(DCacheParameters( 265 nSets = sets, 266 nWays = ways, 267 tagECC = Some("secded"), 268 dataECC = Some("secded"), 269 replacer = Some("setplru"), 270 nMissEntries = 16, 271 nProbeEntries = 8, 272 nReleaseEntries = 18, 273 nMaxPrefetchEntry = 6, 274 enableTagEcc = true, 275 enableDataEcc = true, 276 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 277 )) 278 )) 279}) 280 281case class L2CacheConfig 282( 283 size: String, 284 ways: Int = 8, 285 inclusive: Boolean = true, 286 banks: Int = 1, 287 tp: Boolean = true 288) extends Config((site, here, up) => { 289 case XSTileKey => 290 require(inclusive, "L2 must be inclusive") 291 val nKB = size.toUpperCase() match { 292 case s"${k}KB" => k.strip().toInt 293 case s"${m}MB" => (m.strip().toDouble * 1024).toInt 294 } 295 val upParams = up(XSTileKey) 296 val l2sets = nKB * 1024 / banks / ways / 64 297 upParams.map(p => p.copy( 298 L2CacheParamsOpt = Some(L2Param( 299 name = "L2", 300 ways = ways, 301 sets = l2sets, 302 clientCaches = Seq(L1Param( 303 "dcache", 304 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 305 ways = p.dcacheParametersOpt.get.nWays + 2, 306 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 307 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 308 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 309 )), 310 reqField = Seq(utility.ReqSourceField()), 311 echoField = Seq(huancun.DirtyField()), 312 tagECC = Some("secded"), 313 dataECC = Some("secded"), 314 enableTagECC = true, 315 enableDataECC = true, 316 dataCheck = Some("oddparity"), 317 prefetch = Seq(BOPParameters()) ++ 318 (if (tp) Seq(TPParameters()) else Nil) ++ 319 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 320 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 321 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 322 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 323 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 324 )), 325 L2NBanks = banks 326 )) 327}) 328 329case class L3CacheConfig(size: String, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 330 case SoCParamsKey => 331 val nKB = size.toUpperCase() match { 332 case s"${k}KB" => k.strip().toInt 333 case s"${m}MB" => (m.strip().toDouble * 1024).toInt 334 } 335 val sets = nKB * 1024 / banks / ways / 64 336 val tiles = site(XSTileKey) 337 val clientDirBytes = tiles.map{ t => 338 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 339 }.sum 340 up(SoCParamsKey).copy( 341 L3NBanks = banks, 342 L3CacheParamsOpt = Some(HCCacheParameters( 343 name = "L3", 344 level = 3, 345 ways = ways, 346 sets = sets, 347 inclusive = inclusive, 348 clientCaches = tiles.map{ core => 349 val l2params = core.L2CacheParamsOpt.get.toCacheParams 350 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 351 }, 352 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 353 ctrl = Some(CacheCtrl( 354 address = 0x39000000, 355 numCores = tiles.size 356 )), 357 reqField = Seq(utility.ReqSourceField()), 358 sramClkDivBy2 = true, 359 sramDepthDiv = 4, 360 tagECC = Some("secded"), 361 dataECC = Some("secded"), 362 simulation = !site(DebugOptionsKey).FPGAPlatform, 363 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 364 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 365 )), 366 OpenLLCParamsOpt = Some(OpenLLCParam( 367 name = "LLC", 368 ways = ways, 369 sets = sets, 370 banks = banks, 371 fullAddressBits = 48, 372 clientCaches = tiles.map { core => 373 val l2params = core.L2CacheParamsOpt.get 374 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 375 }, 376 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 377 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 378 )) 379 ) 380}) 381 382class WithL3DebugConfig extends Config( 383 L3CacheConfig("256KB", inclusive = false) ++ L2CacheConfig("64KB") 384) 385 386class MinimalL3DebugConfig(n: Int = 1) extends Config( 387 new WithL3DebugConfig ++ new MinimalConfig(n) 388) 389 390class DefaultL3DebugConfig(n: Int = 1) extends Config( 391 new WithL3DebugConfig ++ new BaseConfig(n) 392) 393 394class WithFuzzer extends Config((site, here, up) => { 395 case DebugOptionsKey => up(DebugOptionsKey).copy( 396 EnablePerfDebug = false, 397 ) 398 case SoCParamsKey => up(SoCParamsKey).copy( 399 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 400 enablePerf = false, 401 )), 402 ) 403 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 404 p.copy( 405 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 406 enablePerf = false, 407 )), 408 ) 409 } 410}) 411 412class MinimalAliasDebugConfig(n: Int = 1) extends Config( 413 L3CacheConfig("512KB", inclusive = false) 414 ++ L2CacheConfig("256KB", inclusive = true) 415 ++ WithNKBL1D(128) 416 ++ new MinimalConfig(n) 417) 418 419class MediumConfig(n: Int = 1) extends Config( 420 L3CacheConfig("4MB", inclusive = false, banks = 4) 421 ++ L2CacheConfig("512KB", inclusive = true) 422 ++ WithNKBL1D(128) 423 ++ new BaseConfig(n) 424) 425 426class FuzzConfig(dummy: Int = 0) extends Config( 427 new WithFuzzer 428 ++ new DefaultConfig(1) 429) 430 431class DefaultConfig(n: Int = 1) extends Config( 432 L3CacheConfig("16MB", inclusive = false, banks = 4, ways = 16) 433 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 434 ++ WithNKBL1D(64, ways = 4) 435 ++ new BaseConfig(n) 436) 437 438class WithCHI extends Config((_, _, _) => { 439 case EnableCHI => true 440}) 441 442class KunminghuV2Config(n: Int = 1) extends Config( 443 new WithCHI 444 ++ new Config((site, here, up) => { 445 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 446 }) 447 ++ L2CacheConfig("1MB", inclusive = true, banks = 4, tp = false) 448 ++ WithNKBL1D(64, ways = 4) 449 ++ new DefaultConfig(n) 450) 451 452class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 453 new WithCHI 454 ++ new Config((site, here, up) => { 455 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 456 }) 457 ++ L2CacheConfig("128KB", inclusive = true, banks = 1, tp = false) 458 ++ WithNKBL1D(32, ways = 4) 459 ++ new MinimalConfig(n) 460) 461 462class XSNoCTopConfig(n: Int = 1) extends Config( 463 (new KunminghuV2Config(n)).alter((site, here, up) => { 464 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 465 }) 466) 467 468class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 469 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 470 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 471 }) 472) 473 474class FpgaDefaultConfig(n: Int = 1) extends Config( 475 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 476 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 477 ++ WithNKBL1D(64, ways = 4) 478 ++ new BaseConfig(n)).alter((site, here, up) => { 479 case DebugOptionsKey => up(DebugOptionsKey).copy( 480 AlwaysBasicDiff = false, 481 AlwaysBasicDB = false 482 ) 483 case SoCParamsKey => up(SoCParamsKey).copy( 484 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 485 sramClkDivBy2 = false, 486 )), 487 ) 488 }) 489) 490 491class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 492 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 493 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 494 ++ WithNKBL1D(64, ways = 8) 495 ++ new BaseConfig(n)).alter((site, here, up) => { 496 case DebugOptionsKey => up(DebugOptionsKey).copy( 497 AlwaysBasicDiff = true, 498 AlwaysBasicDB = false 499 ) 500 case SoCParamsKey => up(SoCParamsKey).copy( 501 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 502 sramClkDivBy2 = false, 503 )), 504 ) 505 }) 506) 507