1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package top 19 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25import system._ 26import org.chipsalliance.cde.config._ 27import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, MaxHartIdBits, XLen} 28import xiangshan.frontend.icache.ICacheParameters 29import freechips.rocketchip.devices.debug._ 30import openLLC.OpenLLCParam 31import freechips.rocketchip.diplomacy._ 32import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 33import xiangshan.cache.DCacheParameters 34import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 35import device.EnableJtag 36import huancun._ 37import coupledL2._ 38import coupledL2.prefetch._ 39 40class BaseConfig(n: Int) extends Config((site, here, up) => { 41 case XLen => 64 42 case DebugOptionsKey => DebugOptions() 43 case SoCParamsKey => SoCParameters() 44 case PMParameKey => PMParameters() 45 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 46 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 47 case DebugModuleKey => Some(DebugModuleParams( 48 nAbstractDataWords = (if (site(XLen) == 32) 1 else if (site(XLen) == 64) 2 else 4), 49 maxSupportedSBAccess = site(XLen), 50 hasBusMaster = true, 51 baseAddress = BigInt(0x38020000), 52 nScratch = 2, 53 crossingHasSafeReset = false, 54 hasHartResets = true 55 )) 56 case JtagDTMKey => JtagDTMKey 57 case MaxHartIdBits => log2Up(n) max 6 58 case EnableJtag => true.B 59}) 60 61// Synthesizable minimal XiangShan 62// * It is still an out-of-order, super-scalaer arch 63// * L1 cache included 64// * L2 cache NOT included 65// * L3 cache included 66class MinimalConfig(n: Int = 1) extends Config( 67 new BaseConfig(n).alter((site, here, up) => { 68 case XSTileKey => up(XSTileKey).map( 69 p => p.copy( 70 DecodeWidth = 6, 71 RenameWidth = 6, 72 RobCommitWidth = 8, 73 FetchWidth = 4, 74 VirtualLoadQueueSize = 24, 75 LoadQueueRARSize = 24, 76 LoadQueueRAWSize = 12, 77 LoadQueueReplaySize = 24, 78 LoadUncacheBufferSize = 8, 79 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 80 RollbackGroupSize = 8, 81 StoreQueueSize = 20, 82 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 83 StoreQueueForwardWithMask = true, 84 // ============ VLSU ============ 85 VlMergeBufferSize = 16, 86 VsMergeBufferSize = 8, 87 UopWritebackWidth = 2, 88 // ============================== 89 RobSize = 48, 90 RabSize = 96, 91 FtqSize = 8, 92 IBufSize = 24, 93 IBufNBank = 6, 94 StoreBufferSize = 4, 95 StoreBufferThreshold = 3, 96 IssueQueueSize = 10, 97 IssueQueueCompEntrySize = 4, 98 intPreg = IntPregParams( 99 numEntries = 64, 100 numRead = None, 101 numWrite = None, 102 ), 103 vfPreg = VfPregParams( 104 numEntries = 160, 105 numRead = None, 106 numWrite = None, 107 ), 108 icacheParameters = ICacheParameters( 109 nSets = 64, // 16KB ICache 110 tagECC = Some("parity"), 111 dataECC = Some("parity"), 112 replacer = Some("setplru"), 113 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)), 114 ), 115 dcacheParametersOpt = Some(DCacheParameters( 116 nSets = 64, // 32KB DCache 117 nWays = 8, 118 tagECC = Some("secded"), 119 dataECC = Some("secded"), 120 replacer = Some("setplru"), 121 nMissEntries = 4, 122 nProbeEntries = 4, 123 nReleaseEntries = 8, 124 nMaxPrefetchEntry = 2, 125 enableTagEcc = true, 126 enableDataEcc = true, 127 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 128 )), 129 // ============ BPU =============== 130 EnableLoop = false, 131 EnableGHistDiff = false, 132 FtbSize = 256, 133 FtbWays = 2, 134 RasSize = 8, 135 RasSpecSize = 16, 136 TageTableInfos = 137 Seq((512, 4, 6), 138 (512, 9, 6), 139 (1024, 19, 6)), 140 SCNRows = 128, 141 SCNTables = 2, 142 SCHistLens = Seq(0, 5), 143 ITTageTableInfos = 144 Seq((256, 4, 7), 145 (256, 8, 7), 146 (512, 16, 7)), 147 // ================================ 148 itlbParameters = TLBParameters( 149 name = "itlb", 150 fetchi = true, 151 useDmode = false, 152 NWays = 4, 153 ), 154 ldtlbParameters = TLBParameters( 155 name = "ldtlb", 156 NWays = 4, 157 partialStaticPMP = true, 158 outsideRecvFlush = true, 159 outReplace = false, 160 lgMaxSize = 4 161 ), 162 sttlbParameters = TLBParameters( 163 name = "sttlb", 164 NWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false, 168 lgMaxSize = 4 169 ), 170 hytlbParameters = TLBParameters( 171 name = "hytlb", 172 NWays = 4, 173 partialStaticPMP = true, 174 outsideRecvFlush = true, 175 outReplace = false, 176 lgMaxSize = 4 177 ), 178 pftlbParameters = TLBParameters( 179 name = "pftlb", 180 NWays = 4, 181 partialStaticPMP = true, 182 outsideRecvFlush = true, 183 outReplace = false, 184 lgMaxSize = 4 185 ), 186 btlbParameters = TLBParameters( 187 name = "btlb", 188 NWays = 4, 189 ), 190 l2tlbParameters = L2TLBParameters( 191 l3Size = 4, 192 l2Size = 4, 193 l1nSets = 4, 194 l1nWays = 4, 195 l1ReservedBits = 1, 196 l0nSets = 4, 197 l0nWays = 8, 198 l0ReservedBits = 0, 199 spSize = 4, 200 ), 201 L2CacheParamsOpt = Some(L2Param( 202 name = "L2", 203 ways = 8, 204 sets = 128, 205 echoField = Seq(huancun.DirtyField()), 206 prefetch = Nil, 207 clientCaches = Seq(L1Param( 208 "dcache", 209 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 210 )), 211 )), 212 L2NBanks = 2, 213 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 214 ) 215 ) 216 case SoCParamsKey => 217 val tiles = site(XSTileKey) 218 up(SoCParamsKey).copy( 219 L3CacheParamsOpt = Option.when(!up(EnableCHI))(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 220 sets = 1024, 221 inclusive = false, 222 clientCaches = tiles.map{ core => 223 val clientDirBytes = tiles.map{ t => 224 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 225 }.sum 226 val l2params = core.L2CacheParamsOpt.get.toCacheParams 227 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 228 }, 229 simulation = !site(DebugOptionsKey).FPGAPlatform, 230 prefetch = None 231 )), 232 OpenLLCParamsOpt = Option.when(up(EnableCHI))(OpenLLCParam( 233 name = "LLC", 234 ways = 8, 235 sets = 2048, 236 banks = 4, 237 clientCaches = Seq(L2Param()) 238 )), 239 L3NBanks = 1 240 ) 241 }) 242) 243 244// Non-synthesizable MinimalConfig, for fast simulation only 245class MinimalSimConfig(n: Int = 1) extends Config( 246 new MinimalConfig(n).alter((site, here, up) => { 247 case XSTileKey => up(XSTileKey).map(_.copy( 248 dcacheParametersOpt = None, 249 softPTW = true 250 )) 251 case SoCParamsKey => up(SoCParamsKey).copy( 252 L3CacheParamsOpt = None, 253 OpenLLCParamsOpt = None 254 ) 255 }) 256) 257 258case class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 259 case XSTileKey => 260 val sets = n * 1024 / ways / 64 261 up(XSTileKey).map(_.copy( 262 dcacheParametersOpt = Some(DCacheParameters( 263 nSets = sets, 264 nWays = ways, 265 tagECC = Some("secded"), 266 dataECC = Some("secded"), 267 replacer = Some("setplru"), 268 nMissEntries = 16, 269 nProbeEntries = 8, 270 nReleaseEntries = 18, 271 nMaxPrefetchEntry = 6, 272 enableTagEcc = true, 273 enableDataEcc = true, 274 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 275 )) 276 )) 277}) 278 279case class L2CacheConfig 280( 281 size: String, 282 ways: Int = 8, 283 inclusive: Boolean = true, 284 banks: Int = 1, 285 tp: Boolean = true 286) extends Config((site, here, up) => { 287 case XSTileKey => 288 require(inclusive, "L2 must be inclusive") 289 val nKB = size.toUpperCase() match { 290 case s"${k}KB" => k.trim().toInt 291 case s"${m}MB" => (m.trim().toDouble * 1024).toInt 292 } 293 val upParams = up(XSTileKey) 294 val l2sets = nKB * 1024 / banks / ways / 64 295 upParams.map(p => p.copy( 296 L2CacheParamsOpt = Some(L2Param( 297 name = "L2", 298 ways = ways, 299 sets = l2sets, 300 clientCaches = Seq(L1Param( 301 "dcache", 302 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 303 ways = p.dcacheParametersOpt.get.nWays + 2, 304 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 305 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 306 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 307 )), 308 reqField = Seq(utility.ReqSourceField()), 309 echoField = Seq(huancun.DirtyField()), 310 tagECC = Some("secded"), 311 dataECC = Some("secded"), 312 enableTagECC = true, 313 enableDataECC = true, 314 dataCheck = Some("oddparity"), 315 enablePoison = true, 316 prefetch = Seq(BOPParameters()) ++ 317 (if (tp) Seq(TPParameters()) else Nil) ++ 318 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 319 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 320 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 321 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 322 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 323 )), 324 L2NBanks = banks 325 )) 326}) 327 328case class L3CacheConfig(size: String, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 329 case SoCParamsKey => 330 val nKB = size.toUpperCase() match { 331 case s"${k}KB" => k.trim().toInt 332 case s"${m}MB" => (m.trim().toDouble * 1024).toInt 333 } 334 val sets = nKB * 1024 / banks / ways / 64 335 val tiles = site(XSTileKey) 336 val clientDirBytes = tiles.map{ t => 337 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 338 }.sum 339 up(SoCParamsKey).copy( 340 L3NBanks = banks, 341 L3CacheParamsOpt = Option.when(!up(EnableCHI))(HCCacheParameters( 342 name = "L3", 343 level = 3, 344 ways = ways, 345 sets = sets, 346 inclusive = inclusive, 347 clientCaches = tiles.map{ core => 348 val l2params = core.L2CacheParamsOpt.get.toCacheParams 349 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 350 }, 351 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 352 ctrl = Some(CacheCtrl( 353 address = 0x39000000, 354 numCores = tiles.size 355 )), 356 reqField = Seq(utility.ReqSourceField()), 357 sramClkDivBy2 = true, 358 sramDepthDiv = 4, 359 tagECC = Some("secded"), 360 dataECC = Some("secded"), 361 simulation = !site(DebugOptionsKey).FPGAPlatform, 362 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 363 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 364 )), 365 OpenLLCParamsOpt = Option.when(up(EnableCHI))(OpenLLCParam( 366 name = "LLC", 367 ways = ways, 368 sets = sets, 369 banks = banks, 370 fullAddressBits = 48, 371 clientCaches = tiles.map { core => 372 val l2params = core.L2CacheParamsOpt.get 373 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 374 }, 375 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 376 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 377 )) 378 ) 379}) 380 381class WithL3DebugConfig extends Config( 382 L3CacheConfig("256KB", inclusive = false) ++ L2CacheConfig("64KB") 383) 384 385class MinimalL3DebugConfig(n: Int = 1) extends Config( 386 new WithL3DebugConfig ++ new MinimalConfig(n) 387) 388 389class DefaultL3DebugConfig(n: Int = 1) extends Config( 390 new WithL3DebugConfig ++ new BaseConfig(n) 391) 392 393class WithFuzzer extends Config((site, here, up) => { 394 case DebugOptionsKey => up(DebugOptionsKey).copy( 395 EnablePerfDebug = false, 396 ) 397 case SoCParamsKey => up(SoCParamsKey).copy( 398 L3CacheParamsOpt = up(SoCParamsKey).L3CacheParamsOpt.map(_.copy( 399 enablePerf = false, 400 )), 401 OpenLLCParamsOpt = up(SoCParamsKey).OpenLLCParamsOpt.map(_.copy( 402 enablePerf = false, 403 )), 404 ) 405 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 406 p.copy( 407 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 408 enablePerf = false, 409 )), 410 ) 411 } 412}) 413 414class MinimalAliasDebugConfig(n: Int = 1) extends Config( 415 L3CacheConfig("512KB", inclusive = false) 416 ++ L2CacheConfig("256KB", inclusive = true) 417 ++ WithNKBL1D(128) 418 ++ new MinimalConfig(n) 419) 420 421class MediumConfig(n: Int = 1) extends Config( 422 L3CacheConfig("4MB", inclusive = false, banks = 4) 423 ++ L2CacheConfig("512KB", inclusive = true) 424 ++ WithNKBL1D(128) 425 ++ new BaseConfig(n) 426) 427 428class FuzzConfig(dummy: Int = 0) extends Config( 429 new WithFuzzer 430 ++ new DefaultConfig(1) 431) 432 433class DefaultConfig(n: Int = 1) extends Config( 434 L3CacheConfig("16MB", inclusive = false, banks = 4, ways = 16) 435 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 436 ++ WithNKBL1D(64, ways = 4) 437 ++ new BaseConfig(n) 438) 439 440class WithCHI extends Config((_, _, _) => { 441 case EnableCHI => true 442}) 443 444class KunminghuV2Config(n: Int = 1) extends Config( 445 L2CacheConfig("1MB", inclusive = true, banks = 4, tp = false) 446 ++ new DefaultConfig(n) 447 ++ new WithCHI 448) 449 450class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 451 L2CacheConfig("128KB", inclusive = true, banks = 1, tp = false) 452 ++ WithNKBL1D(32, ways = 4) 453 ++ new MinimalConfig(n) 454 ++ new WithCHI 455) 456 457class XSNoCTopConfig(n: Int = 1) extends Config( 458 (new KunminghuV2Config(n)).alter((site, here, up) => { 459 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 460 }) 461) 462 463class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 464 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 465 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 466 }) 467) 468 469class XSNoCDiffTopConfig(n: Int = 1) extends Config( 470 (new XSNoCTopConfig(n)).alter((site, here, up) => { 471 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCDiffTop = true) 472 }) 473) 474 475class XSNoCDiffTopMinimalConfig(n: Int = 1) extends Config( 476 (new XSNoCTopConfig(n)).alter((site, here, up) => { 477 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCDiffTop = true) 478 }) 479) 480 481class FpgaDefaultConfig(n: Int = 1) extends Config( 482 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 483 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 484 ++ WithNKBL1D(64, ways = 4) 485 ++ new BaseConfig(n)).alter((site, here, up) => { 486 case DebugOptionsKey => up(DebugOptionsKey).copy( 487 AlwaysBasicDiff = false, 488 AlwaysBasicDB = false 489 ) 490 case SoCParamsKey => up(SoCParamsKey).copy( 491 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 492 sramClkDivBy2 = false, 493 )), 494 ) 495 }) 496) 497 498class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 499 (L3CacheConfig("3MB", inclusive = false, banks = 1, ways = 6) 500 ++ L2CacheConfig("1MB", inclusive = true, banks = 4) 501 ++ WithNKBL1D(64, ways = 4) 502 ++ new BaseConfig(n)).alter((site, here, up) => { 503 case DebugOptionsKey => up(DebugOptionsKey).copy( 504 AlwaysBasicDiff = true, 505 AlwaysBasicDB = false 506 ) 507 case SoCParamsKey => up(SoCParamsKey).copy( 508 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 509 sramClkDivBy2 = false, 510 )), 511 ) 512 }) 513) 514