1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import freechips.rocketchip.devices.debug._ 27import freechips.rocketchip.tile.MaxHartIdBits 28import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 32import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 33import xiangshan.cache.mmu.{L2TLBParameters} 34import device.{XSDebugModuleParams, EnableJtag} 35 36class DefaultConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters( 40 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 41 ) 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => false.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new DefaultConfig(n).alter((site, here, up) => { 56 case SoCParamsKey => up(SoCParamsKey).copy( 57 cores = up(SoCParamsKey).cores.map(_.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RoqSize = 32, 66 BrqSize = 8, 67 FtqSize = 8, 68 IBufSize = 16, 69 StoreBufferSize = 4, 70 StoreBufferThreshold = 3, 71 dpParams = DispatchParameters( 72 IntDqSize = 12, 73 FpDqSize = 12, 74 LsDqSize = 12, 75 IntDqDeqWidth = 4, 76 FpDqDeqWidth = 4, 77 LsDqDeqWidth = 4 78 ), 79 exuParameters = ExuParameters( 80 JmpCnt = 1, 81 AluCnt = 2, 82 MulCnt = 0, 83 MduCnt = 1, 84 FmacCnt = 1, 85 FmiscCnt = 1, 86 FmiscDivSqrtCnt = 0, 87 LduCnt = 2, 88 StuCnt = 2 89 ), 90 icacheParameters = ICacheParameters( 91 nSets = 64, // 16KB ICache 92 tagECC = Some("parity"), 93 dataECC = Some("parity"), 94 replacer = Some("setplru"), 95 nMissEntries = 2 96 ), 97 dcacheParameters = DCacheParameters( 98 nSets = 64, // 32KB DCache 99 nWays = 8, 100 tagECC = Some("secded"), 101 dataECC = Some("secded"), 102 replacer = Some("setplru"), 103 nMissEntries = 4, 104 nProbeEntries = 4, 105 nReleaseEntries = 4, 106 nStoreReplayEntries = 4, 107 ), 108 EnableBPD = false, // disable TAGE 109 EnableLoop = false, 110 TlbEntrySize = 32, 111 TlbSPEntrySize = 4, 112 l2tlbParameters = L2TLBParameters( 113 l1Size = 4, 114 l2nSets = 4, 115 l2nWays = 4, 116 l3nSets = 4, 117 l3nWays = 8, 118 spSize = 2, 119 missQueueSize = 8 120 ), 121 useFakeL2Cache = true, // disable L2 Cache 122 )), 123 L3Size = 256 * 1024, // 256KB L3 Cache 124 ) 125 }) 126) 127 128// Non-synthesizable MinimalConfig, for fast simulation only 129class MinimalSimConfig(n: Int = 1) extends Config( 130 new MinimalConfig(n).alter((site, here, up) => { 131 case SoCParamsKey => up(SoCParamsKey).copy( 132 cores = up(SoCParamsKey).cores.map(_.copy( 133 useFakeDCache = true, 134 useFakePTW = true, 135 useFakeL1plusCache = true, 136 )), 137 useFakeL3Cache = true 138 ) 139 }) 140) 141