1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import openLLC.{OpenLLCParam} 35import xiangshan._ 36import xiangshan.backend.dispatch.DispatchParameters 37import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 38import xiangshan.cache.DCacheParameters 39import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 40import device.{EnableJtag, XSDebugModuleParams} 41import huancun._ 42import coupledL2._ 43import coupledL2.prefetch._ 44import xiangshan.frontend.icache.ICacheParameters 45 46class BaseConfig(n: Int) extends Config((site, here, up) => { 47 case XLen => 64 48 case DebugOptionsKey => DebugOptions() 49 case SoCParamsKey => SoCParameters() 50 case PMParameKey => PMParameters() 51 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 52 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 53 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 54 case JtagDTMKey => JtagDTMKey 55 case MaxHartIdBits => log2Up(n) max 6 56 case EnableJtag => true.B 57}) 58 59// Synthesizable minimal XiangShan 60// * It is still an out-of-order, super-scalaer arch 61// * L1 cache included 62// * L2 cache NOT included 63// * L3 cache included 64class MinimalConfig(n: Int = 1) extends Config( 65 new BaseConfig(n).alter((site, here, up) => { 66 case XSTileKey => up(XSTileKey).map( 67 p => p.copy( 68 DecodeWidth = 6, 69 RenameWidth = 6, 70 RobCommitWidth = 8, 71 FetchWidth = 4, 72 VirtualLoadQueueSize = 24, 73 LoadQueueRARSize = 24, 74 LoadQueueRAWSize = 12, 75 LoadQueueReplaySize = 24, 76 LoadUncacheBufferSize = 8, 77 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 78 RollbackGroupSize = 8, 79 StoreQueueSize = 20, 80 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 81 StoreQueueForwardWithMask = true, 82 // ============ VLSU ============ 83 VlMergeBufferSize = 16, 84 VsMergeBufferSize = 8, 85 UopWritebackWidth = 2, 86 // ============================== 87 RobSize = 48, 88 RabSize = 96, 89 FtqSize = 8, 90 IBufSize = 24, 91 IBufNBank = 6, 92 StoreBufferSize = 4, 93 StoreBufferThreshold = 3, 94 IssueQueueSize = 10, 95 IssueQueueCompEntrySize = 4, 96 dpParams = DispatchParameters( 97 IntDqSize = 12, 98 FpDqSize = 12, 99 LsDqSize = 12, 100 IntDqDeqWidth = 8, 101 FpDqDeqWidth = 6, 102 VecDqDeqWidth = 6, 103 LsDqDeqWidth = 6 104 ), 105 intPreg = IntPregParams( 106 numEntries = 64, 107 numRead = None, 108 numWrite = None, 109 ), 110 vfPreg = VfPregParams( 111 numEntries = 160, 112 numRead = None, 113 numWrite = None, 114 ), 115 icacheParameters = ICacheParameters( 116 nSets = 64, // 16KB ICache 117 tagECC = Some("parity"), 118 dataECC = Some("parity"), 119 replacer = Some("setplru"), 120 ), 121 dcacheParametersOpt = Some(DCacheParameters( 122 nSets = 64, // 32KB DCache 123 nWays = 8, 124 tagECC = Some("secded"), 125 dataECC = Some("secded"), 126 replacer = Some("setplru"), 127 nMissEntries = 4, 128 nProbeEntries = 4, 129 nReleaseEntries = 8, 130 nMaxPrefetchEntry = 2, 131 enableTagEcc = true, 132 enableDataEcc = true, 133 )), 134 // ============ BPU =============== 135 EnableLoop = false, 136 EnableGHistDiff = false, 137 FtbSize = 256, 138 FtbWays = 2, 139 RasSize = 8, 140 RasSpecSize = 16, 141 TageTableInfos = 142 Seq((512, 4, 6), 143 (512, 9, 6), 144 (1024, 19, 6)), 145 SCNRows = 128, 146 SCNTables = 2, 147 SCHistLens = Seq(0, 5), 148 ITTageTableInfos = 149 Seq((256, 4, 7), 150 (256, 8, 7), 151 (512, 16, 7)), 152 // ================================ 153 itlbParameters = TLBParameters( 154 name = "itlb", 155 fetchi = true, 156 useDmode = false, 157 NWays = 4, 158 ), 159 ldtlbParameters = TLBParameters( 160 name = "ldtlb", 161 NWays = 4, 162 partialStaticPMP = true, 163 outsideRecvFlush = true, 164 outReplace = false, 165 lgMaxSize = 4 166 ), 167 sttlbParameters = TLBParameters( 168 name = "sttlb", 169 NWays = 4, 170 partialStaticPMP = true, 171 outsideRecvFlush = true, 172 outReplace = false, 173 lgMaxSize = 4 174 ), 175 hytlbParameters = TLBParameters( 176 name = "hytlb", 177 NWays = 4, 178 partialStaticPMP = true, 179 outsideRecvFlush = true, 180 outReplace = false, 181 lgMaxSize = 4 182 ), 183 pftlbParameters = TLBParameters( 184 name = "pftlb", 185 NWays = 4, 186 partialStaticPMP = true, 187 outsideRecvFlush = true, 188 outReplace = false, 189 lgMaxSize = 4 190 ), 191 btlbParameters = TLBParameters( 192 name = "btlb", 193 NWays = 4, 194 ), 195 l2tlbParameters = L2TLBParameters( 196 l3Size = 4, 197 l2Size = 4, 198 l1nSets = 4, 199 l1nWays = 4, 200 l1ReservedBits = 1, 201 l0nSets = 4, 202 l0nWays = 8, 203 l0ReservedBits = 0, 204 spSize = 4, 205 ), 206 L2CacheParamsOpt = Some(L2Param( 207 name = "L2", 208 ways = 8, 209 sets = 128, 210 echoField = Seq(huancun.DirtyField()), 211 prefetch = Nil, 212 clientCaches = Seq(L1Param( 213 "dcache", 214 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 215 )), 216 )), 217 L2NBanks = 2, 218 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 219 ) 220 ) 221 case SoCParamsKey => 222 val tiles = site(XSTileKey) 223 up(SoCParamsKey).copy( 224 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 225 sets = 1024, 226 inclusive = false, 227 clientCaches = tiles.map{ core => 228 val clientDirBytes = tiles.map{ t => 229 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 230 }.sum 231 val l2params = core.L2CacheParamsOpt.get.toCacheParams 232 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 233 }, 234 simulation = !site(DebugOptionsKey).FPGAPlatform, 235 prefetch = None 236 )), 237 L3NBanks = 1 238 ) 239 }) 240) 241 242// Non-synthesizable MinimalConfig, for fast simulation only 243class MinimalSimConfig(n: Int = 1) extends Config( 244 new MinimalConfig(n).alter((site, here, up) => { 245 case XSTileKey => up(XSTileKey).map(_.copy( 246 dcacheParametersOpt = None, 247 softPTW = true 248 )) 249 case SoCParamsKey => up(SoCParamsKey).copy( 250 L3CacheParamsOpt = None 251 ) 252 }) 253) 254 255class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 256 case XSTileKey => 257 val sets = n * 1024 / ways / 64 258 up(XSTileKey).map(_.copy( 259 dcacheParametersOpt = Some(DCacheParameters( 260 nSets = sets, 261 nWays = ways, 262 tagECC = Some("secded"), 263 dataECC = Some("secded"), 264 replacer = Some("setplru"), 265 nMissEntries = 16, 266 nProbeEntries = 8, 267 nReleaseEntries = 18, 268 nMaxPrefetchEntry = 6, 269 enableTagEcc = true, 270 enableDataEcc = true 271 )) 272 )) 273}) 274 275class WithNKBL2 276( 277 n: Int, 278 ways: Int = 8, 279 inclusive: Boolean = true, 280 banks: Int = 1, 281 tp: Boolean = true 282) extends Config((site, here, up) => { 283 case XSTileKey => 284 require(inclusive, "L2 must be inclusive") 285 val upParams = up(XSTileKey) 286 val l2sets = n * 1024 / banks / ways / 64 287 upParams.map(p => p.copy( 288 L2CacheParamsOpt = Some(L2Param( 289 name = "L2", 290 ways = ways, 291 sets = l2sets, 292 clientCaches = Seq(L1Param( 293 "dcache", 294 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 295 ways = p.dcacheParametersOpt.get.nWays + 2, 296 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 297 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 298 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 299 )), 300 reqField = Seq(utility.ReqSourceField()), 301 echoField = Seq(huancun.DirtyField()), 302 tagECC = Some("secded"), 303 dataECC = Some("secded"), 304 enableTagECC = true, 305 enableDataECC = true, 306 dataCheck = Some("oddparity"), 307 prefetch = Seq(BOPParameters()) ++ 308 (if (tp) Seq(TPParameters()) else Nil) ++ 309 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 310 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 311 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 312 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 313 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 314 )), 315 L2NBanks = banks 316 )) 317}) 318 319class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 320 case SoCParamsKey => 321 val sets = n * 1024 / banks / ways / 64 322 val tiles = site(XSTileKey) 323 val clientDirBytes = tiles.map{ t => 324 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 325 }.sum 326 up(SoCParamsKey).copy( 327 L3NBanks = banks, 328 L3CacheParamsOpt = Some(HCCacheParameters( 329 name = "L3", 330 level = 3, 331 ways = ways, 332 sets = sets, 333 inclusive = inclusive, 334 clientCaches = tiles.map{ core => 335 val l2params = core.L2CacheParamsOpt.get.toCacheParams 336 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 337 }, 338 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 339 ctrl = Some(CacheCtrl( 340 address = 0x39000000, 341 numCores = tiles.size 342 )), 343 reqField = Seq(utility.ReqSourceField()), 344 sramClkDivBy2 = true, 345 sramDepthDiv = 4, 346 tagECC = Some("secded"), 347 dataECC = Some("secded"), 348 simulation = !site(DebugOptionsKey).FPGAPlatform, 349 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 350 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 351 )), 352 OpenLLCParamsOpt = Some(OpenLLCParam( 353 name = "LLC", 354 ways = ways, 355 sets = sets, 356 banks = banks, 357 fullAddressBits = 48, 358 clientCaches = tiles.map { core => 359 val l2params = core.L2CacheParamsOpt.get 360 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 361 } 362 )) 363 ) 364}) 365 366class WithL3DebugConfig extends Config( 367 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 368) 369 370class MinimalL3DebugConfig(n: Int = 1) extends Config( 371 new WithL3DebugConfig ++ new MinimalConfig(n) 372) 373 374class DefaultL3DebugConfig(n: Int = 1) extends Config( 375 new WithL3DebugConfig ++ new BaseConfig(n) 376) 377 378class WithFuzzer extends Config((site, here, up) => { 379 case DebugOptionsKey => up(DebugOptionsKey).copy( 380 EnablePerfDebug = false, 381 ) 382 case SoCParamsKey => up(SoCParamsKey).copy( 383 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 384 enablePerf = false, 385 )), 386 ) 387 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 388 p.copy( 389 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 390 enablePerf = false, 391 )), 392 ) 393 } 394}) 395 396class MinimalAliasDebugConfig(n: Int = 1) extends Config( 397 new WithNKBL3(512, inclusive = false) ++ 398 new WithNKBL2(256, inclusive = true) ++ 399 new WithNKBL1D(128) ++ 400 new MinimalConfig(n) 401) 402 403class MediumConfig(n: Int = 1) extends Config( 404 new WithNKBL3(4096, inclusive = false, banks = 4) 405 ++ new WithNKBL2(512, inclusive = true) 406 ++ new WithNKBL1D(128) 407 ++ new BaseConfig(n) 408) 409 410class FuzzConfig(dummy: Int = 0) extends Config( 411 new WithFuzzer 412 ++ new DefaultConfig(1) 413) 414 415class DefaultConfig(n: Int = 1) extends Config( 416 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 417 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 418 ++ new WithNKBL1D(64, ways = 4) 419 ++ new BaseConfig(n) 420) 421 422class WithCHI extends Config((_, _, _) => { 423 case EnableCHI => true 424}) 425 426class KunminghuV2Config(n: Int = 1) extends Config( 427 new WithCHI 428 ++ new Config((site, here, up) => { 429 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 430 }) 431 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 432 ++ new WithNKBL1D(64, ways = 4) 433 ++ new DefaultConfig(n) 434) 435 436class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 437 new WithCHI 438 ++ new Config((site, here, up) => { 439 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 440 }) 441 ++ new WithNKBL2(128, inclusive = true, banks = 1, tp = false) 442 ++ new WithNKBL1D(32, ways = 4) 443 ++ new MinimalConfig(n) 444) 445 446class XSNoCTopConfig(n: Int = 1) extends Config( 447 (new KunminghuV2Config(n)).alter((site, here, up) => { 448 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 449 }) 450) 451 452class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 453 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 454 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 455 }) 456) 457 458class FpgaDefaultConfig(n: Int = 1) extends Config( 459 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 460 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 461 ++ new WithNKBL1D(64, ways = 4) 462 ++ new BaseConfig(n)).alter((site, here, up) => { 463 case DebugOptionsKey => up(DebugOptionsKey).copy( 464 AlwaysBasicDiff = false, 465 AlwaysBasicDB = false 466 ) 467 case SoCParamsKey => up(SoCParamsKey).copy( 468 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 469 sramClkDivBy2 = false, 470 )), 471 ) 472 }) 473) 474 475class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 476 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 477 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 478 ++ new WithNKBL1D(64, ways = 8) 479 ++ new BaseConfig(n)).alter((site, here, up) => { 480 case DebugOptionsKey => up(DebugOptionsKey).copy( 481 AlwaysBasicDiff = true, 482 AlwaysBasicDB = false 483 ) 484 case SoCParamsKey => up(SoCParamsKey).copy( 485 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 486 sramClkDivBy2 = false, 487 )), 488 ) 489 }) 490) 491