xref: /XiangShan/src/main/scala/top/Configs.scala (revision a273862e37f1d43bee748f2a6353320a2f52f6f4) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import system._
24import chipsalliance.rocketchip.config._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
26import xiangshan.frontend.ICacheParameters
27import freechips.rocketchip.devices.debug._
28import freechips.rocketchip.tile.MaxHartIdBits
29import xiangshan.backend.dispatch.DispatchParameters
30import xiangshan.backend.exu.ExuParameters
31import xiangshan.cache.DCacheParameters
32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
33import device.{EnableJtag, XSDebugModuleParams}
34import huancun._
35
36class BaseConfig(n: Int) extends Config((site, here, up) => {
37  case XLen => 64
38  case DebugOptionsKey => DebugOptions()
39  case SoCParamsKey => SoCParameters(
40    cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) }
41  )
42  case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
43  case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
44  case JtagDTMKey => JtagDTMKey
45  case MaxHartIdBits => 2
46  case EnableJtag => false.B
47})
48
49// Synthesizable minimal XiangShan
50// * It is still an out-of-order, super-scalaer arch
51// * L1 cache included
52// * L2 cache NOT included
53// * L3 cache included
54class MinimalConfig(n: Int = 1) extends Config(
55  new BaseConfig(n).alter((site, here, up) => {
56    case SoCParamsKey => up(SoCParamsKey).copy(
57      cores = up(SoCParamsKey).cores.map(_.copy(
58        DecodeWidth = 2,
59        RenameWidth = 2,
60        FetchWidth = 4,
61        IssQueSize = 8,
62        NRPhyRegs = 64,
63        LoadQueueSize = 16,
64        StoreQueueSize = 12,
65        RobSize = 32,
66        FtqSize = 8,
67        IBufSize = 16,
68        StoreBufferSize = 4,
69        StoreBufferThreshold = 3,
70        dpParams = DispatchParameters(
71          IntDqSize = 12,
72          FpDqSize = 12,
73          LsDqSize = 12,
74          IntDqDeqWidth = 4,
75          FpDqDeqWidth = 4,
76          LsDqDeqWidth = 4
77        ),
78        exuParameters = ExuParameters(
79          JmpCnt = 1,
80          AluCnt = 2,
81          MulCnt = 0,
82          MduCnt = 1,
83          FmacCnt = 1,
84          FmiscCnt = 1,
85          FmiscDivSqrtCnt = 0,
86          LduCnt = 2,
87          StuCnt = 2
88        ),
89        icacheParameters = ICacheParameters(
90          nSets = 64, // 16KB ICache
91          tagECC = Some("parity"),
92          dataECC = Some("parity"),
93          replacer = Some("setplru"),
94          nMissEntries = 2
95        ),
96        dcacheParametersOpt = Some(DCacheParameters(
97          nSets = 64, // 32KB DCache
98          nWays = 8,
99          tagECC = Some("secded"),
100          dataECC = Some("secded"),
101          replacer = Some("setplru"),
102          nMissEntries = 4,
103          nProbeEntries = 4,
104          nReleaseEntries = 8,
105        )),
106        EnableBPD = false, // disable TAGE
107        EnableLoop = false,
108        itlbParameters = TLBParameters(
109          name = "itlb",
110          fetchi = true,
111          useDmode = false,
112          sameCycle = true,
113          normalReplacer = Some("plru"),
114          superReplacer = Some("plru"),
115          normalNWays = 4,
116          normalNSets = 1,
117          superNWays = 2,
118          shouldBlock = true
119        ),
120        ldtlbParameters = TLBParameters(
121          name = "ldtlb",
122          normalNSets = 4, // when da or sa
123          normalNWays = 1, // when fa or sa
124          normalAssociative = "sa",
125          normalReplacer = Some("setplru"),
126          superNWays = 4,
127          normalAsVictim = true,
128          outReplace = true
129        ),
130        sttlbParameters = TLBParameters(
131          name = "sttlb",
132          normalNSets = 4, // when da or sa
133          normalNWays = 1, // when fa or sa
134          normalAssociative = "sa",
135          normalReplacer = Some("setplru"),
136          normalAsVictim = true,
137          superNWays = 4,
138          outReplace = true
139        ),
140        btlbParameters = TLBParameters(
141          name = "btlb",
142          normalNSets = 1,
143          normalNWays = 8,
144          superNWays = 2
145        ),
146        l2tlbParameters = L2TLBParameters(
147          l1Size = 4,
148          l2nSets = 4,
149          l2nWays = 4,
150          l3nSets = 4,
151          l3nWays = 8,
152          spSize = 2,
153        ),
154        L2CacheParamsOpt = None // remove L2 Cache
155      )),
156      L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
157        sets = 1024
158      )),
159      L3NBanks = 1
160    )
161  })
162)
163
164// Non-synthesizable MinimalConfig, for fast simulation only
165class MinimalSimConfig(n: Int = 1) extends Config(
166  new MinimalConfig(n).alter((site, here, up) => {
167    case SoCParamsKey => up(SoCParamsKey).copy(
168      cores = up(SoCParamsKey).cores.map(_.copy(
169        dcacheParametersOpt = None,
170        softPTW = true
171      )),
172      L3CacheParamsOpt = None
173    )
174  })
175)
176
177class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
178  case SoCParamsKey =>
179    val upParams = up(SoCParamsKey)
180    val sets = n * 1024 / ways / 64
181    upParams.copy(cores = upParams.cores.map(p => p.copy(
182      dcacheParametersOpt = Some(DCacheParameters(
183        nSets = sets,
184        nWays = ways,
185        tagECC = Some("secded"),
186        dataECC = Some("secded"),
187        replacer = Some("setplru"),
188        nMissEntries = 16,
189        nProbeEntries = 16,
190        nReleaseEntries = 32
191      ))
192    )))
193})
194
195class WithNKBL2
196(
197  n: Int,
198  ways: Int = 8,
199  inclusive: Boolean = true,
200  banks: Int = 1,
201  alwaysReleaseData: Boolean = false
202) extends Config((site, here, up) => {
203  case SoCParamsKey =>
204    val upParams = up(SoCParamsKey)
205    val l2sets = n * 1024 / banks / ways / 64
206    upParams.copy(
207      cores = upParams.cores.map(p => p.copy(
208        L2CacheParamsOpt = Some(HCCacheParameters(
209          name = "L2",
210          level = 2,
211          ways = ways,
212          sets = l2sets,
213          inclusive = inclusive,
214          alwaysReleaseData = alwaysReleaseData,
215          clientCaches = Seq(CacheParameters(
216            "dcache",
217            sets = 2 * p.dcacheParametersOpt.get.nSets,
218            ways = p.dcacheParametersOpt.get.nWays + 2,
219            aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
220          )),
221          reqField = Seq(PreferCacheField()),
222          echoField = Seq(DirtyField()),
223          prefetch = Some(huancun.prefetch.BOPParameters()),
224          enablePerf = true
225        )
226      ), L2NBanks = banks
227      ))
228    )
229})
230
231class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
232  case SoCParamsKey =>
233    val upParams = up(SoCParamsKey)
234    val sets = n * 1024 / banks / ways / 64
235    upParams.copy(
236      L3NBanks = banks,
237      L3CacheParamsOpt = Some(HCCacheParameters(
238        name = "L3",
239        level = 3,
240        ways = ways,
241        sets = sets,
242        inclusive = inclusive,
243        clientCaches = upParams.cores.map{ core =>
244          val l2params = core.L2CacheParamsOpt.get.toCacheParams
245          l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways)
246        },
247        enablePerf = true
248      ))
249    )
250})
251
252class WithL3DebugConfig extends Config(
253  new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
254)
255
256class MinimalL3DebugConfig(n: Int = 1) extends Config(
257  new WithL3DebugConfig ++ new MinimalConfig(n)
258)
259
260class DefaultL3DebugConfig(n: Int = 1) extends Config(
261  new WithL3DebugConfig ++ new BaseConfig(n)
262)
263
264class MinimalAliasDebugConfig(n: Int = 1) extends Config(
265  new WithNKBL3(512, inclusive = false) ++
266    new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++
267    new WithNKBL1D(128) ++
268    new MinimalConfig(n)
269)
270
271class MediumConfig(n: Int = 1) extends Config(
272  new WithNKBL3(4096, inclusive = false, banks = 4)
273    ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true)
274    ++ new WithNKBL1D(128)
275    ++ new BaseConfig(n)
276)
277
278class DefaultConfig(n: Int = 1) extends Config(
279  new WithNKBL3(10 * 1024, inclusive = false, banks = 4, ways = 10)
280    ++ new WithNKBL2(2 * 512, inclusive = false, banks = 2, alwaysReleaseData = true)
281    ++ new WithNKBL1D(128)
282    ++ new BaseConfig(n)
283)
284