1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.{ICacheParameters} 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import xiangshan.cache.prefetch._ 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun.{CacheParameters, HCCacheParameters} 36 37class DefaultConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters( 41 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 ) 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => false.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new DefaultConfig(n).alter((site, here, up) => { 57 case SoCParamsKey => up(SoCParamsKey).copy( 58 cores = up(SoCParamsKey).cores.map(_.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 FetchWidth = 4, 62 IssQueSize = 8, 63 NRPhyRegs = 64, 64 LoadQueueSize = 16, 65 StoreQueueSize = 12, 66 RoqSize = 32, 67 BrqSize = 8, 68 FtqSize = 8, 69 IBufSize = 16, 70 StoreBufferSize = 4, 71 StoreBufferThreshold = 3, 72 dpParams = DispatchParameters( 73 IntDqSize = 12, 74 FpDqSize = 12, 75 LsDqSize = 12, 76 IntDqDeqWidth = 4, 77 FpDqDeqWidth = 4, 78 LsDqDeqWidth = 4 79 ), 80 exuParameters = ExuParameters( 81 JmpCnt = 1, 82 AluCnt = 2, 83 MulCnt = 0, 84 MduCnt = 1, 85 FmacCnt = 1, 86 FmiscCnt = 1, 87 FmiscDivSqrtCnt = 0, 88 LduCnt = 2, 89 StuCnt = 2 90 ), 91 icacheParameters = ICacheParameters( 92 nSets = 64, // 16KB ICache 93 tagECC = Some("parity"), 94 dataECC = Some("parity"), 95 replacer = Some("setplru"), 96 nMissEntries = 2 97 ), 98 dcacheParameters = DCacheParameters( 99 nSets = 64, // 32KB DCache 100 nWays = 8, 101 tagECC = Some("secded"), 102 dataECC = Some("secded"), 103 replacer = Some("setplru"), 104 nMissEntries = 4, 105 nProbeEntries = 4, 106 nReleaseEntries = 4, 107 nStoreReplayEntries = 4, 108 ), 109 EnableBPD = false, // disable TAGE 110 EnableLoop = false, 111 itlbParameters = TLBParameters( 112 name = "itlb", 113 fetchi = true, 114 useDmode = false, 115 sameCycle = true, 116 normalReplacer = Some("plru"), 117 superReplacer = Some("plru"), 118 normalNWays = 4, 119 normalNSets = 1, 120 superNWays = 2, 121 shouldBlock = true 122 ), 123 ldtlbParameters = TLBParameters( 124 name = "ldtlb", 125 normalNSets = 4, // when da or sa 126 normalNWays = 1, // when fa or sa 127 normalAssociative = "sa", 128 normalReplacer = Some("setplru"), 129 superNWays = 4, 130 normalAsVictim = true, 131 outReplace = true 132 ), 133 sttlbParameters = TLBParameters( 134 name = "sttlb", 135 normalNSets = 4, // when da or sa 136 normalNWays = 1, // when fa or sa 137 normalAssociative = "sa", 138 normalReplacer = Some("setplru"), 139 normalAsVictim = true, 140 superNWays = 4, 141 outReplace = true 142 ), 143 btlbParameters = TLBParameters( 144 name = "btlb", 145 normalNSets = 1, 146 normalNWays = 8, 147 superNWays = 2 148 ), 149 l2tlbParameters = L2TLBParameters( 150 l1Size = 4, 151 l2nSets = 4, 152 l2nWays = 4, 153 l3nSets = 4, 154 l3nWays = 8, 155 spSize = 2, 156 missQueueSize = 8 157 ), 158 useFakeL2Cache = true, // disable L2 Cache 159 )), 160 L3CacheParams = up(SoCParamsKey).L3CacheParams.copy( 161 sets = 1024 162 ), 163 L3NBanks = 1 164 ) 165 }) 166) 167 168// Non-synthesizable MinimalConfig, for fast simulation only 169class MinimalSimConfig(n: Int = 1) extends Config( 170 new MinimalConfig(n).alter((site, here, up) => { 171 case SoCParamsKey => up(SoCParamsKey).copy( 172 cores = up(SoCParamsKey).cores.map(_.copy( 173 useFakeDCache = true, 174 useFakePTW = true, 175 useFakeL1plusCache = true, 176 )), 177 useFakeL3Cache = true 178 ) 179 }) 180) 181 182class WithNKBL2(n: Int, ways: Int = 8, inclusive: Boolean = true) extends Config((site, here, up) => { 183 case SoCParamsKey => 184 val upParams = up(SoCParamsKey) 185 val l2sets = n * 1024 / ways / 64 186 upParams.copy( 187 cores = upParams.cores.map(p => p.copy( 188 L2CacheParams = HCCacheParameters( 189 name = "L2", 190 level = 2, 191 ways = ways, 192 sets = l2sets, 193 inclusive = inclusive, 194 prefetch = Some(huancun.prefetch.BOPParameters()) 195 ), 196 useFakeL2Cache = false, 197 useFakeDCache = false, 198 useFakePTW = false, 199 useFakeL1plusCache = false 200 )) 201 ) 202}) 203 204class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 205 case SoCParamsKey => 206 val upParams = up(SoCParamsKey) 207 val sets = n * 1024 / banks / ways / 64 208 upParams.copy( 209 L3NBanks = banks, 210 L3CacheParams = HCCacheParameters( 211 name = "L3", 212 level = 3, 213 ways = ways, 214 sets = sets, 215 inclusive = inclusive, 216 clientCaches = upParams.cores.map{ core => 217 val l2params = core.L2CacheParams.toCacheParams 218 l2params.copy(ways = 2 * l2params.ways) 219 } 220 ) 221 ) 222}) 223 224class WithL3DebugConfig extends Config( 225 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 226) 227 228class MinimalL3DebugConfig(n: Int = 1) extends Config( 229 new WithL3DebugConfig ++ new MinimalConfig(n) 230) 231 232class DefaultL3DebugConfig(n: Int = 1) extends Config( 233 new WithL3DebugConfig ++ new DefaultConfig(n) 234) 235 236class NonInclusiveL3Config(n: Int = 1) extends Config( 237 new WithNKBL3(4096, inclusive = false, banks = 4) ++ new WithNKBL2(512) ++ new DefaultConfig(n) 238) 239