1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36 37class BaseConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters() 41 case PMParameKey => PMParameters() 42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => true.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new BaseConfig(n).alter((site, here, up) => { 57 case XSTileKey => up(XSTileKey).map( 58 _.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 CommitWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 64, 65 LoadQueueSize = 16, 66 LoadQueueNWriteBanks = 4, 67 StoreQueueSize = 12, 68 StoreQueueNWriteBanks = 4, 69 RobSize = 32, 70 FtqSize = 8, 71 IBufSize = 16, 72 StoreBufferSize = 4, 73 StoreBufferThreshold = 3, 74 dpParams = DispatchParameters( 75 IntDqSize = 12, 76 FpDqSize = 12, 77 LsDqSize = 12, 78 IntDqDeqWidth = 4, 79 FpDqDeqWidth = 4, 80 LsDqDeqWidth = 4 81 ), 82 exuParameters = ExuParameters( 83 JmpCnt = 1, 84 AluCnt = 2, 85 MulCnt = 0, 86 MduCnt = 1, 87 FmacCnt = 1, 88 FmiscCnt = 1, 89 FmiscDivSqrtCnt = 0, 90 LduCnt = 2, 91 StuCnt = 2 92 ), 93 icacheParameters = ICacheParameters( 94 nSets = 64, // 16KB ICache 95 tagECC = Some("parity"), 96 dataECC = Some("parity"), 97 replacer = Some("setplru"), 98 nMissEntries = 2, 99 nReleaseEntries = 1, 100 nProbeEntries = 2, 101 nPrefetchEntries = 2, 102 hasPrefetch = false 103 ), 104 dcacheParametersOpt = Some(DCacheParameters( 105 nSets = 64, // 32KB DCache 106 nWays = 8, 107 tagECC = Some("secded"), 108 dataECC = Some("secded"), 109 replacer = Some("setplru"), 110 nMissEntries = 4, 111 nProbeEntries = 4, 112 nReleaseEntries = 8, 113 )), 114 EnableBPD = false, // disable TAGE 115 EnableLoop = false, 116 itlbParameters = TLBParameters( 117 name = "itlb", 118 fetchi = true, 119 useDmode = false, 120 normalReplacer = Some("plru"), 121 superReplacer = Some("plru"), 122 normalNWays = 4, 123 normalNSets = 1, 124 superNWays = 2 125 ), 126 ldtlbParameters = TLBParameters( 127 name = "ldtlb", 128 normalNSets = 16, // when da or sa 129 normalNWays = 1, // when fa or sa 130 normalAssociative = "sa", 131 normalReplacer = Some("setplru"), 132 superNWays = 4, 133 normalAsVictim = true, 134 partialStaticPMP = true, 135 outsideRecvFlush = true, 136 outReplace = false 137 ), 138 sttlbParameters = TLBParameters( 139 name = "sttlb", 140 normalNSets = 16, // when da or sa 141 normalNWays = 1, // when fa or sa 142 normalAssociative = "sa", 143 normalReplacer = Some("setplru"), 144 normalAsVictim = true, 145 superNWays = 4, 146 partialStaticPMP = true, 147 outsideRecvFlush = true, 148 outReplace = false 149 ), 150 btlbParameters = TLBParameters( 151 name = "btlb", 152 normalNSets = 1, 153 normalNWays = 8, 154 superNWays = 2 155 ), 156 l2tlbParameters = L2TLBParameters( 157 l1Size = 4, 158 l2nSets = 4, 159 l2nWays = 4, 160 l3nSets = 4, 161 l3nWays = 8, 162 spSize = 2, 163 ), 164 L2CacheParamsOpt = None, // remove L2 Cache 165 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 166 ) 167 ) 168 case SoCParamsKey => 169 val tiles = site(XSTileKey) 170 up(SoCParamsKey).copy( 171 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 172 sets = 1024, 173 inclusive = false, 174 clientCaches = tiles.map{ p => 175 CacheParameters( 176 "dcache", 177 sets = 2 * p.dcacheParametersOpt.get.nSets, 178 ways = p.dcacheParametersOpt.get.nWays + 2, 179 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 180 aliasBitsOpt = None 181 ) 182 }, 183 simulation = !site(DebugOptionsKey).FPGAPlatform 184 )), 185 L3NBanks = 1 186 ) 187 }) 188) 189 190// Non-synthesizable MinimalConfig, for fast simulation only 191class MinimalSimConfig(n: Int = 1) extends Config( 192 new MinimalConfig(n).alter((site, here, up) => { 193 case XSTileKey => up(XSTileKey).map(_.copy( 194 dcacheParametersOpt = None, 195 softPTW = true 196 )) 197 case SoCParamsKey => up(SoCParamsKey).copy( 198 L3CacheParamsOpt = None 199 ) 200 }) 201) 202 203class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 204 case XSTileKey => 205 val sets = n * 1024 / ways / 64 206 up(XSTileKey).map(_.copy( 207 dcacheParametersOpt = Some(DCacheParameters( 208 nSets = sets, 209 nWays = ways, 210 tagECC = Some("secded"), 211 dataECC = Some("secded"), 212 replacer = Some("setplru"), 213 nMissEntries = 16, 214 nProbeEntries = 8, 215 nReleaseEntries = 18 216 )) 217 )) 218}) 219 220class WithNKBL2 221( 222 n: Int, 223 ways: Int = 8, 224 inclusive: Boolean = true, 225 banks: Int = 1, 226 alwaysReleaseData: Boolean = false 227) extends Config((site, here, up) => { 228 case XSTileKey => 229 val upParams = up(XSTileKey) 230 val l2sets = n * 1024 / banks / ways / 64 231 upParams.map(p => p.copy( 232 L2CacheParamsOpt = Some(HCCacheParameters( 233 name = "L2", 234 level = 2, 235 ways = ways, 236 sets = l2sets, 237 inclusive = inclusive, 238 alwaysReleaseData = alwaysReleaseData, 239 clientCaches = Seq(CacheParameters( 240 "dcache", 241 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 242 ways = p.dcacheParametersOpt.get.nWays + 2, 243 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 244 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 245 )), 246 reqField = Seq(PreferCacheField()), 247 echoField = Seq(DirtyField()), 248 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 249 enablePerf = true, 250 sramDepthDiv = 2, 251 tagECC = Some("secded"), 252 dataECC = Some("secded"), 253 simulation = !site(DebugOptionsKey).FPGAPlatform 254 )), 255 L2NBanks = banks 256 )) 257}) 258 259class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 260 case SoCParamsKey => 261 val sets = n * 1024 / banks / ways / 64 262 val tiles = site(XSTileKey) 263 val clientDirBytes = tiles.map{ t => 264 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 265 }.sum 266 up(SoCParamsKey).copy( 267 L3NBanks = banks, 268 L3CacheParamsOpt = Some(HCCacheParameters( 269 name = "L3", 270 level = 3, 271 ways = ways, 272 sets = sets, 273 inclusive = inclusive, 274 clientCaches = tiles.map{ core => 275 val l2params = core.L2CacheParamsOpt.get.toCacheParams 276 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 277 }, 278 enablePerf = true, 279 ctrl = Some(CacheCtrl( 280 address = 0x39000000, 281 numCores = tiles.size 282 )), 283 sramClkDivBy2 = true, 284 sramDepthDiv = 4, 285 tagECC = Some("secded"), 286 dataECC = Some("secded"), 287 simulation = !site(DebugOptionsKey).FPGAPlatform 288 )) 289 ) 290}) 291 292class WithL3DebugConfig extends Config( 293 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 294) 295 296class MinimalL3DebugConfig(n: Int = 1) extends Config( 297 new WithL3DebugConfig ++ new MinimalConfig(n) 298) 299 300class DefaultL3DebugConfig(n: Int = 1) extends Config( 301 new WithL3DebugConfig ++ new BaseConfig(n) 302) 303 304class MinimalAliasDebugConfig(n: Int = 1) extends Config( 305 new WithNKBL3(512, inclusive = false) ++ 306 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 307 new WithNKBL1D(128) ++ 308 new MinimalConfig(n) 309) 310 311class MediumConfig(n: Int = 1) extends Config( 312 new WithNKBL3(4096, inclusive = false, banks = 4) 313 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 314 ++ new WithNKBL1D(128) 315 ++ new BaseConfig(n) 316) 317 318class DefaultConfig(n: Int = 1) extends Config( 319 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 320 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 321 ++ new WithNKBL1D(128) 322 ++ new BaseConfig(n) 323) 324