1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import coupledL2.prefetch._ 43import xiangshan.frontend.icache.ICacheParameters 44 45class BaseConfig(n: Int) extends Config((site, here, up) => { 46 case XLen => 64 47 case DebugOptionsKey => DebugOptions() 48 case SoCParamsKey => SoCParameters() 49 case PMParameKey => PMParameters() 50 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 51 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 52 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 53 case JtagDTMKey => JtagDTMKey 54 case MaxHartIdBits => log2Up(n) max 6 55 case EnableJtag => true.B 56}) 57 58// Synthesizable minimal XiangShan 59// * It is still an out-of-order, super-scalaer arch 60// * L1 cache included 61// * L2 cache NOT included 62// * L3 cache included 63class MinimalConfig(n: Int = 1) extends Config( 64 new BaseConfig(n).alter((site, here, up) => { 65 case XSTileKey => up(XSTileKey).map( 66 p => p.copy( 67 DecodeWidth = 6, 68 RenameWidth = 6, 69 RobCommitWidth = 8, 70 FetchWidth = 4, 71 VirtualLoadQueueSize = 24, 72 LoadQueueRARSize = 24, 73 LoadQueueRAWSize = 12, 74 LoadQueueReplaySize = 24, 75 LoadUncacheBufferSize = 8, 76 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 77 RollbackGroupSize = 8, 78 StoreQueueSize = 20, 79 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 80 StoreQueueForwardWithMask = true, 81 // ============ VLSU ============ 82 VlMergeBufferSize = 8, 83 VsMergeBufferSize = 8, 84 UopWritebackWidth = 2, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 10, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 6, 101 VecDqDeqWidth = 6, 102 LsDqDeqWidth = 6 103 ), 104 intPreg = IntPregParams( 105 numEntries = 64, 106 numRead = None, 107 numWrite = None, 108 ), 109 vfPreg = VfPregParams( 110 numEntries = 160, 111 numRead = None, 112 numWrite = None, 113 ), 114 icacheParameters = ICacheParameters( 115 nSets = 64, // 16KB ICache 116 tagECC = Some("parity"), 117 dataECC = Some("parity"), 118 replacer = Some("setplru"), 119 nMissEntries = 2, 120 nReleaseEntries = 1, 121 nProbeEntries = 2, 122 // fdip 123 enableICachePrefetch = true, 124 prefetchToL1 = false, 125 ), 126 dcacheParametersOpt = Some(DCacheParameters( 127 nSets = 64, // 32KB DCache 128 nWays = 8, 129 tagECC = Some("secded"), 130 dataECC = Some("secded"), 131 replacer = Some("setplru"), 132 nMissEntries = 4, 133 nProbeEntries = 4, 134 nReleaseEntries = 8, 135 nMaxPrefetchEntry = 2, 136 )), 137 // ============ BPU =============== 138 EnableLoop = false, 139 EnableGHistDiff = false, 140 FtbSize = 256, 141 FtbWays = 2, 142 RasSize = 8, 143 RasSpecSize = 16, 144 TageTableInfos = 145 Seq((512, 4, 6), 146 (512, 9, 6), 147 (1024, 19, 6)), 148 SCNRows = 128, 149 SCNTables = 2, 150 SCHistLens = Seq(0, 5), 151 ITTageTableInfos = 152 Seq((256, 4, 7), 153 (256, 8, 7), 154 (512, 16, 7)), 155 // ================================ 156 itlbParameters = TLBParameters( 157 name = "itlb", 158 fetchi = true, 159 useDmode = false, 160 NWays = 4, 161 ), 162 ldtlbParameters = TLBParameters( 163 name = "ldtlb", 164 NWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false, 168 lgMaxSize = 4 169 ), 170 sttlbParameters = TLBParameters( 171 name = "sttlb", 172 NWays = 4, 173 partialStaticPMP = true, 174 outsideRecvFlush = true, 175 outReplace = false, 176 lgMaxSize = 4 177 ), 178 hytlbParameters = TLBParameters( 179 name = "hytlb", 180 NWays = 4, 181 partialStaticPMP = true, 182 outsideRecvFlush = true, 183 outReplace = false, 184 lgMaxSize = 4 185 ), 186 pftlbParameters = TLBParameters( 187 name = "pftlb", 188 NWays = 4, 189 partialStaticPMP = true, 190 outsideRecvFlush = true, 191 outReplace = false, 192 lgMaxSize = 4 193 ), 194 btlbParameters = TLBParameters( 195 name = "btlb", 196 NWays = 4, 197 ), 198 l2tlbParameters = L2TLBParameters( 199 l1Size = 4, 200 l2nSets = 4, 201 l2nWays = 4, 202 l3nSets = 4, 203 l3nWays = 8, 204 spSize = 2, 205 ), 206 L2CacheParamsOpt = Some(L2Param( 207 name = "L2", 208 ways = 8, 209 sets = 128, 210 echoField = Seq(huancun.DirtyField()), 211 prefetch = Nil, 212 clientCaches = Seq(L1Param( 213 "dcache", 214 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 215 )), 216 )), 217 L2NBanks = 2, 218 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 219 ) 220 ) 221 case SoCParamsKey => 222 val tiles = site(XSTileKey) 223 up(SoCParamsKey).copy( 224 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 225 sets = 1024, 226 inclusive = false, 227 clientCaches = tiles.map{ core => 228 val clientDirBytes = tiles.map{ t => 229 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 230 }.sum 231 val l2params = core.L2CacheParamsOpt.get.toCacheParams 232 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 233 }, 234 simulation = !site(DebugOptionsKey).FPGAPlatform, 235 prefetch = None 236 )), 237 L3NBanks = 1 238 ) 239 }) 240) 241 242// Non-synthesizable MinimalConfig, for fast simulation only 243class MinimalSimConfig(n: Int = 1) extends Config( 244 new MinimalConfig(n).alter((site, here, up) => { 245 case XSTileKey => up(XSTileKey).map(_.copy( 246 dcacheParametersOpt = None, 247 softPTW = true 248 )) 249 case SoCParamsKey => up(SoCParamsKey).copy( 250 L3CacheParamsOpt = None 251 ) 252 }) 253) 254 255class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 256 case XSTileKey => 257 val sets = n * 1024 / ways / 64 258 up(XSTileKey).map(_.copy( 259 dcacheParametersOpt = Some(DCacheParameters( 260 nSets = sets, 261 nWays = ways, 262 tagECC = Some("secded"), 263 dataECC = Some("secded"), 264 replacer = Some("setplru"), 265 nMissEntries = 16, 266 nProbeEntries = 8, 267 nReleaseEntries = 18, 268 nMaxPrefetchEntry = 6, 269 )) 270 )) 271}) 272 273class WithNKBL2 274( 275 n: Int, 276 ways: Int = 8, 277 inclusive: Boolean = true, 278 banks: Int = 1, 279 tp: Boolean = true 280) extends Config((site, here, up) => { 281 case XSTileKey => 282 require(inclusive, "L2 must be inclusive") 283 val upParams = up(XSTileKey) 284 val l2sets = n * 1024 / banks / ways / 64 285 upParams.map(p => p.copy( 286 L2CacheParamsOpt = Some(L2Param( 287 name = "L2", 288 ways = ways, 289 sets = l2sets, 290 clientCaches = Seq(L1Param( 291 "dcache", 292 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 293 ways = p.dcacheParametersOpt.get.nWays + 2, 294 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 295 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 296 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 297 )), 298 reqField = Seq(utility.ReqSourceField()), 299 echoField = Seq(huancun.DirtyField()), 300 prefetch = Seq(PrefetchReceiverParams(), BOPParameters()) ++ (if (tp) Seq(TPParameters()) else Nil), 301 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 302 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 303 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 304 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 305 )), 306 L2NBanks = banks 307 )) 308}) 309 310class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 311 case SoCParamsKey => 312 val sets = n * 1024 / banks / ways / 64 313 val tiles = site(XSTileKey) 314 val clientDirBytes = tiles.map{ t => 315 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 316 }.sum 317 up(SoCParamsKey).copy( 318 L3NBanks = banks, 319 L3CacheParamsOpt = Some(HCCacheParameters( 320 name = "L3", 321 level = 3, 322 ways = ways, 323 sets = sets, 324 inclusive = inclusive, 325 clientCaches = tiles.map{ core => 326 val l2params = core.L2CacheParamsOpt.get.toCacheParams 327 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 328 }, 329 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 330 ctrl = Some(CacheCtrl( 331 address = 0x39000000, 332 numCores = tiles.size 333 )), 334 reqField = Seq(utility.ReqSourceField()), 335 sramClkDivBy2 = true, 336 sramDepthDiv = 4, 337 tagECC = Some("secded"), 338 dataECC = Some("secded"), 339 simulation = !site(DebugOptionsKey).FPGAPlatform, 340 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 341 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 342 )) 343 ) 344}) 345 346class WithL3DebugConfig extends Config( 347 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 348) 349 350class MinimalL3DebugConfig(n: Int = 1) extends Config( 351 new WithL3DebugConfig ++ new MinimalConfig(n) 352) 353 354class DefaultL3DebugConfig(n: Int = 1) extends Config( 355 new WithL3DebugConfig ++ new BaseConfig(n) 356) 357 358class WithFuzzer extends Config((site, here, up) => { 359 case DebugOptionsKey => up(DebugOptionsKey).copy( 360 EnablePerfDebug = false, 361 ) 362 case SoCParamsKey => up(SoCParamsKey).copy( 363 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 364 enablePerf = false, 365 )), 366 ) 367 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 368 p.copy( 369 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 370 enablePerf = false, 371 )), 372 ) 373 } 374}) 375 376class MinimalAliasDebugConfig(n: Int = 1) extends Config( 377 new WithNKBL3(512, inclusive = false) ++ 378 new WithNKBL2(256, inclusive = true) ++ 379 new WithNKBL1D(128) ++ 380 new MinimalConfig(n) 381) 382 383class MediumConfig(n: Int = 1) extends Config( 384 new WithNKBL3(4096, inclusive = false, banks = 4) 385 ++ new WithNKBL2(512, inclusive = true) 386 ++ new WithNKBL1D(128) 387 ++ new BaseConfig(n) 388) 389 390class FuzzConfig(dummy: Int = 0) extends Config( 391 new WithFuzzer 392 ++ new DefaultConfig(1) 393) 394 395class DefaultConfig(n: Int = 1) extends Config( 396 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 397 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 398 ++ new WithNKBL1D(64, ways = 8) 399 ++ new BaseConfig(n) 400) 401 402class WithCHI extends Config((_, _, _) => { 403 case EnableCHI => true 404}) 405 406class KunminghuV2Config(n: Int = 1) extends Config( 407 new WithCHI 408 ++ new Config((site, here, up) => { 409 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 410 }) 411 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 412 ++ new WithNKBL1D(64, ways = 8) 413 ++ new BaseConfig(n) 414)