1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import coupledL2.prefetch._ 43import xiangshan.frontend.icache.ICacheParameters 44 45class BaseConfig(n: Int) extends Config((site, here, up) => { 46 case XLen => 64 47 case DebugOptionsKey => DebugOptions() 48 case SoCParamsKey => SoCParameters() 49 case PMParameKey => PMParameters() 50 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 51 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 52 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 53 case JtagDTMKey => JtagDTMKey 54 case MaxHartIdBits => log2Up(n) max 6 55 case EnableJtag => true.B 56}) 57 58// Synthesizable minimal XiangShan 59// * It is still an out-of-order, super-scalaer arch 60// * L1 cache included 61// * L2 cache NOT included 62// * L3 cache included 63class MinimalConfig(n: Int = 1) extends Config( 64 new BaseConfig(n).alter((site, here, up) => { 65 case XSTileKey => up(XSTileKey).map( 66 p => p.copy( 67 DecodeWidth = 6, 68 RenameWidth = 6, 69 RobCommitWidth = 8, 70 FetchWidth = 4, 71 VirtualLoadQueueSize = 24, 72 LoadQueueRARSize = 24, 73 LoadQueueRAWSize = 12, 74 LoadQueueReplaySize = 24, 75 LoadUncacheBufferSize = 8, 76 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 77 RollbackGroupSize = 8, 78 StoreQueueSize = 20, 79 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 80 StoreQueueForwardWithMask = true, 81 // ============ VLSU ============ 82 VlMergeBufferSize = 16, 83 VsMergeBufferSize = 8, 84 UopWritebackWidth = 2, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 10, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 6, 101 VecDqDeqWidth = 6, 102 LsDqDeqWidth = 6 103 ), 104 intPreg = IntPregParams( 105 numEntries = 64, 106 numRead = None, 107 numWrite = None, 108 ), 109 vfPreg = VfPregParams( 110 numEntries = 160, 111 numRead = None, 112 numWrite = None, 113 ), 114 icacheParameters = ICacheParameters( 115 nSets = 64, // 16KB ICache 116 tagECC = Some("parity"), 117 dataECC = Some("parity"), 118 replacer = Some("setplru"), 119 ), 120 dcacheParametersOpt = Some(DCacheParameters( 121 nSets = 64, // 32KB DCache 122 nWays = 8, 123 tagECC = Some("secded"), 124 dataECC = Some("secded"), 125 replacer = Some("setplru"), 126 nMissEntries = 4, 127 nProbeEntries = 4, 128 nReleaseEntries = 8, 129 nMaxPrefetchEntry = 2, 130 )), 131 // ============ BPU =============== 132 EnableLoop = false, 133 EnableGHistDiff = false, 134 FtbSize = 256, 135 FtbWays = 2, 136 RasSize = 8, 137 RasSpecSize = 16, 138 TageTableInfos = 139 Seq((512, 4, 6), 140 (512, 9, 6), 141 (1024, 19, 6)), 142 SCNRows = 128, 143 SCNTables = 2, 144 SCHistLens = Seq(0, 5), 145 ITTageTableInfos = 146 Seq((256, 4, 7), 147 (256, 8, 7), 148 (512, 16, 7)), 149 // ================================ 150 itlbParameters = TLBParameters( 151 name = "itlb", 152 fetchi = true, 153 useDmode = false, 154 NWays = 4, 155 ), 156 ldtlbParameters = TLBParameters( 157 name = "ldtlb", 158 NWays = 4, 159 partialStaticPMP = true, 160 outsideRecvFlush = true, 161 outReplace = false, 162 lgMaxSize = 4 163 ), 164 sttlbParameters = TLBParameters( 165 name = "sttlb", 166 NWays = 4, 167 partialStaticPMP = true, 168 outsideRecvFlush = true, 169 outReplace = false, 170 lgMaxSize = 4 171 ), 172 hytlbParameters = TLBParameters( 173 name = "hytlb", 174 NWays = 4, 175 partialStaticPMP = true, 176 outsideRecvFlush = true, 177 outReplace = false, 178 lgMaxSize = 4 179 ), 180 pftlbParameters = TLBParameters( 181 name = "pftlb", 182 NWays = 4, 183 partialStaticPMP = true, 184 outsideRecvFlush = true, 185 outReplace = false, 186 lgMaxSize = 4 187 ), 188 btlbParameters = TLBParameters( 189 name = "btlb", 190 NWays = 4, 191 ), 192 l2tlbParameters = L2TLBParameters( 193 l3Size = 4, 194 l2Size = 4, 195 l1nSets = 4, 196 l1nWays = 4, 197 l0nSets = 4, 198 l0nWays = 8, 199 spSize = 4, 200 ), 201 L2CacheParamsOpt = Some(L2Param( 202 name = "L2", 203 ways = 8, 204 sets = 128, 205 echoField = Seq(huancun.DirtyField()), 206 prefetch = Nil, 207 clientCaches = Seq(L1Param( 208 "dcache", 209 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 210 )), 211 )), 212 L2NBanks = 2, 213 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 214 ) 215 ) 216 case SoCParamsKey => 217 val tiles = site(XSTileKey) 218 up(SoCParamsKey).copy( 219 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 220 sets = 1024, 221 inclusive = false, 222 clientCaches = tiles.map{ core => 223 val clientDirBytes = tiles.map{ t => 224 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 225 }.sum 226 val l2params = core.L2CacheParamsOpt.get.toCacheParams 227 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 228 }, 229 simulation = !site(DebugOptionsKey).FPGAPlatform, 230 prefetch = None 231 )), 232 L3NBanks = 1 233 ) 234 }) 235) 236 237// Non-synthesizable MinimalConfig, for fast simulation only 238class MinimalSimConfig(n: Int = 1) extends Config( 239 new MinimalConfig(n).alter((site, here, up) => { 240 case XSTileKey => up(XSTileKey).map(_.copy( 241 dcacheParametersOpt = None, 242 softPTW = true 243 )) 244 case SoCParamsKey => up(SoCParamsKey).copy( 245 L3CacheParamsOpt = None 246 ) 247 }) 248) 249 250class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 251 case XSTileKey => 252 val sets = n * 1024 / ways / 64 253 up(XSTileKey).map(_.copy( 254 dcacheParametersOpt = Some(DCacheParameters( 255 nSets = sets, 256 nWays = ways, 257 tagECC = Some("secded"), 258 dataECC = Some("secded"), 259 replacer = Some("setplru"), 260 nMissEntries = 16, 261 nProbeEntries = 8, 262 nReleaseEntries = 18, 263 nMaxPrefetchEntry = 6, 264 )) 265 )) 266}) 267 268class WithNKBL2 269( 270 n: Int, 271 ways: Int = 8, 272 inclusive: Boolean = true, 273 banks: Int = 1, 274 tp: Boolean = true 275) extends Config((site, here, up) => { 276 case XSTileKey => 277 require(inclusive, "L2 must be inclusive") 278 val upParams = up(XSTileKey) 279 val l2sets = n * 1024 / banks / ways / 64 280 upParams.map(p => p.copy( 281 L2CacheParamsOpt = Some(L2Param( 282 name = "L2", 283 ways = ways, 284 sets = l2sets, 285 clientCaches = Seq(L1Param( 286 "dcache", 287 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 288 ways = p.dcacheParametersOpt.get.nWays + 2, 289 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 290 vaddrBitsOpt = Some((if(p.EnableSv48) p.VAddrBitsSv48 else p.VAddrBitsSv39) - log2Up(p.dcacheParametersOpt.get.blockBytes)), 291 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 292 )), 293 reqField = Seq(utility.ReqSourceField()), 294 echoField = Seq(huancun.DirtyField()), 295 prefetch = Seq(BOPParameters()) ++ 296 (if (tp) Seq(TPParameters()) else Nil) ++ 297 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 298 hasRVA23CMO = p.HasRVA23CMO, 299 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 300 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 301 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 302 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 303 )), 304 L2NBanks = banks 305 )) 306}) 307 308class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 309 case SoCParamsKey => 310 val sets = n * 1024 / banks / ways / 64 311 val tiles = site(XSTileKey) 312 val clientDirBytes = tiles.map{ t => 313 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 314 }.sum 315 up(SoCParamsKey).copy( 316 L3NBanks = banks, 317 L3CacheParamsOpt = Some(HCCacheParameters( 318 name = "L3", 319 level = 3, 320 ways = ways, 321 sets = sets, 322 inclusive = inclusive, 323 clientCaches = tiles.map{ core => 324 val l2params = core.L2CacheParamsOpt.get.toCacheParams 325 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 326 }, 327 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 328 ctrl = Some(CacheCtrl( 329 address = 0x39000000, 330 numCores = tiles.size 331 )), 332 reqField = Seq(utility.ReqSourceField()), 333 sramClkDivBy2 = true, 334 sramDepthDiv = 4, 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 simulation = !site(DebugOptionsKey).FPGAPlatform, 338 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 339 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 340 )) 341 ) 342}) 343 344class WithL3DebugConfig extends Config( 345 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 346) 347 348class MinimalL3DebugConfig(n: Int = 1) extends Config( 349 new WithL3DebugConfig ++ new MinimalConfig(n) 350) 351 352class DefaultL3DebugConfig(n: Int = 1) extends Config( 353 new WithL3DebugConfig ++ new BaseConfig(n) 354) 355 356class WithFuzzer extends Config((site, here, up) => { 357 case DebugOptionsKey => up(DebugOptionsKey).copy( 358 EnablePerfDebug = false, 359 ) 360 case SoCParamsKey => up(SoCParamsKey).copy( 361 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 362 enablePerf = false, 363 )), 364 ) 365 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 366 p.copy( 367 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 368 enablePerf = false, 369 )), 370 ) 371 } 372}) 373 374class MinimalAliasDebugConfig(n: Int = 1) extends Config( 375 new WithNKBL3(512, inclusive = false) ++ 376 new WithNKBL2(256, inclusive = true) ++ 377 new WithNKBL1D(128) ++ 378 new MinimalConfig(n) 379) 380 381class MediumConfig(n: Int = 1) extends Config( 382 new WithNKBL3(4096, inclusive = false, banks = 4) 383 ++ new WithNKBL2(512, inclusive = true) 384 ++ new WithNKBL1D(128) 385 ++ new BaseConfig(n) 386) 387 388class FuzzConfig(dummy: Int = 0) extends Config( 389 new WithFuzzer 390 ++ new DefaultConfig(1) 391) 392 393class DefaultConfig(n: Int = 1) extends Config( 394 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 395 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 396 ++ new WithNKBL1D(64, ways = 8) 397 ++ new BaseConfig(n) 398) 399 400class WithCHI extends Config((_, _, _) => { 401 case EnableCHI => true 402}) 403 404class KunminghuV2Config(n: Int = 1) extends Config( 405 new WithCHI 406 ++ new Config((site, here, up) => { 407 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 408 }) 409 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 410 ++ new WithNKBL1D(64, ways = 8) 411 ++ new DefaultConfig(n) 412) 413 414class XSNoCTopConfig(n: Int = 1) extends Config( 415 (new KunminghuV2Config(n)).alter((site, here, up) => { 416 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 417 }) 418) 419 420class FpgaDefaultConfig(n: Int = 1) extends Config( 421 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 422 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 423 ++ new WithNKBL1D(64, ways = 8) 424 ++ new BaseConfig(n)).alter((site, here, up) => { 425 case DebugOptionsKey => up(DebugOptionsKey).copy( 426 AlwaysBasicDiff = false, 427 AlwaysBasicDB = false 428 ) 429 case SoCParamsKey => up(SoCParamsKey).copy( 430 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 431 sramClkDivBy2 = false, 432 )), 433 ) 434 }) 435) 436