1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import coupledL2.prefetch._ 43import xiangshan.frontend.icache.ICacheParameters 44 45class BaseConfig(n: Int) extends Config((site, here, up) => { 46 case XLen => 64 47 case DebugOptionsKey => DebugOptions() 48 case SoCParamsKey => SoCParameters() 49 case PMParameKey => PMParameters() 50 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 51 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 52 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 53 case JtagDTMKey => JtagDTMKey 54 case MaxHartIdBits => log2Up(n) max 6 55 case EnableJtag => true.B 56}) 57 58// Synthesizable minimal XiangShan 59// * It is still an out-of-order, super-scalaer arch 60// * L1 cache included 61// * L2 cache NOT included 62// * L3 cache included 63class MinimalConfig(n: Int = 1) extends Config( 64 new BaseConfig(n).alter((site, here, up) => { 65 case XSTileKey => up(XSTileKey).map( 66 p => p.copy( 67 DecodeWidth = 6, 68 RenameWidth = 6, 69 RobCommitWidth = 8, 70 FetchWidth = 4, 71 VirtualLoadQueueSize = 24, 72 LoadQueueRARSize = 24, 73 LoadQueueRAWSize = 12, 74 LoadQueueReplaySize = 24, 75 LoadUncacheBufferSize = 8, 76 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 77 RollbackGroupSize = 8, 78 StoreQueueSize = 20, 79 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 80 StoreQueueForwardWithMask = true, 81 // ============ VLSU ============ 82 VlMergeBufferSize = 16, 83 VsMergeBufferSize = 8, 84 UopWritebackWidth = 2, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 10, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 6, 101 VecDqDeqWidth = 6, 102 LsDqDeqWidth = 6 103 ), 104 intPreg = IntPregParams( 105 numEntries = 64, 106 numRead = None, 107 numWrite = None, 108 ), 109 vfPreg = VfPregParams( 110 numEntries = 160, 111 numRead = None, 112 numWrite = None, 113 ), 114 icacheParameters = ICacheParameters( 115 nSets = 64, // 16KB ICache 116 tagECC = Some("parity"), 117 dataECC = Some("parity"), 118 replacer = Some("setplru"), 119 ), 120 dcacheParametersOpt = Some(DCacheParameters( 121 nSets = 64, // 32KB DCache 122 nWays = 8, 123 tagECC = Some("secded"), 124 dataECC = Some("secded"), 125 replacer = Some("setplru"), 126 nMissEntries = 4, 127 nProbeEntries = 4, 128 nReleaseEntries = 8, 129 nMaxPrefetchEntry = 2, 130 )), 131 // ============ BPU =============== 132 EnableLoop = false, 133 EnableGHistDiff = false, 134 FtbSize = 256, 135 FtbWays = 2, 136 RasSize = 8, 137 RasSpecSize = 16, 138 TageTableInfos = 139 Seq((512, 4, 6), 140 (512, 9, 6), 141 (1024, 19, 6)), 142 SCNRows = 128, 143 SCNTables = 2, 144 SCHistLens = Seq(0, 5), 145 ITTageTableInfos = 146 Seq((256, 4, 7), 147 (256, 8, 7), 148 (512, 16, 7)), 149 // ================================ 150 itlbParameters = TLBParameters( 151 name = "itlb", 152 fetchi = true, 153 useDmode = false, 154 NWays = 4, 155 ), 156 ldtlbParameters = TLBParameters( 157 name = "ldtlb", 158 NWays = 4, 159 partialStaticPMP = true, 160 outsideRecvFlush = true, 161 outReplace = false, 162 lgMaxSize = 4 163 ), 164 sttlbParameters = TLBParameters( 165 name = "sttlb", 166 NWays = 4, 167 partialStaticPMP = true, 168 outsideRecvFlush = true, 169 outReplace = false, 170 lgMaxSize = 4 171 ), 172 hytlbParameters = TLBParameters( 173 name = "hytlb", 174 NWays = 4, 175 partialStaticPMP = true, 176 outsideRecvFlush = true, 177 outReplace = false, 178 lgMaxSize = 4 179 ), 180 pftlbParameters = TLBParameters( 181 name = "pftlb", 182 NWays = 4, 183 partialStaticPMP = true, 184 outsideRecvFlush = true, 185 outReplace = false, 186 lgMaxSize = 4 187 ), 188 btlbParameters = TLBParameters( 189 name = "btlb", 190 NWays = 4, 191 ), 192 l2tlbParameters = L2TLBParameters( 193 l3Size = 4, 194 l2Size = 4, 195 l1nSets = 4, 196 l1nWays = 4, 197 l1ReservedBits = 1, 198 l0nSets = 4, 199 l0nWays = 8, 200 l0ReservedBits = 0, 201 spSize = 4, 202 ), 203 L2CacheParamsOpt = Some(L2Param( 204 name = "L2", 205 ways = 8, 206 sets = 128, 207 echoField = Seq(huancun.DirtyField()), 208 prefetch = Nil, 209 clientCaches = Seq(L1Param( 210 "dcache", 211 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 212 )), 213 hasCMO = p.HasCMO && site(EnableCHI), 214 )), 215 L2NBanks = 2, 216 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 217 ) 218 ) 219 case SoCParamsKey => 220 val tiles = site(XSTileKey) 221 up(SoCParamsKey).copy( 222 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 223 sets = 1024, 224 inclusive = false, 225 clientCaches = tiles.map{ core => 226 val clientDirBytes = tiles.map{ t => 227 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 228 }.sum 229 val l2params = core.L2CacheParamsOpt.get.toCacheParams 230 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 231 }, 232 simulation = !site(DebugOptionsKey).FPGAPlatform, 233 prefetch = None 234 )), 235 L3NBanks = 1 236 ) 237 }) 238) 239 240// Non-synthesizable MinimalConfig, for fast simulation only 241class MinimalSimConfig(n: Int = 1) extends Config( 242 new MinimalConfig(n).alter((site, here, up) => { 243 case XSTileKey => up(XSTileKey).map(_.copy( 244 dcacheParametersOpt = None, 245 softPTW = true 246 )) 247 case SoCParamsKey => up(SoCParamsKey).copy( 248 L3CacheParamsOpt = None 249 ) 250 }) 251) 252 253class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 254 case XSTileKey => 255 val sets = n * 1024 / ways / 64 256 up(XSTileKey).map(_.copy( 257 dcacheParametersOpt = Some(DCacheParameters( 258 nSets = sets, 259 nWays = ways, 260 tagECC = Some("secded"), 261 dataECC = Some("secded"), 262 replacer = Some("setplru"), 263 nMissEntries = 16, 264 nProbeEntries = 8, 265 nReleaseEntries = 18, 266 nMaxPrefetchEntry = 6, 267 )) 268 )) 269}) 270 271class WithNKBL2 272( 273 n: Int, 274 ways: Int = 8, 275 inclusive: Boolean = true, 276 banks: Int = 1, 277 tp: Boolean = true 278) extends Config((site, here, up) => { 279 case XSTileKey => 280 require(inclusive, "L2 must be inclusive") 281 val upParams = up(XSTileKey) 282 val l2sets = n * 1024 / banks / ways / 64 283 upParams.map(p => p.copy( 284 L2CacheParamsOpt = Some(L2Param( 285 name = "L2", 286 ways = ways, 287 sets = l2sets, 288 clientCaches = Seq(L1Param( 289 "dcache", 290 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 291 ways = p.dcacheParametersOpt.get.nWays + 2, 292 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 293 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 294 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 295 )), 296 reqField = Seq(utility.ReqSourceField()), 297 echoField = Seq(huancun.DirtyField()), 298 prefetch = Seq(BOPParameters()) ++ 299 (if (tp) Seq(TPParameters()) else Nil) ++ 300 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 301 hasCMO = p.HasCMO && site(EnableCHI), 302 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 303 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 304 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 305 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 306 )), 307 L2NBanks = banks 308 )) 309}) 310 311class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 312 case SoCParamsKey => 313 val sets = n * 1024 / banks / ways / 64 314 val tiles = site(XSTileKey) 315 val clientDirBytes = tiles.map{ t => 316 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 317 }.sum 318 up(SoCParamsKey).copy( 319 L3NBanks = banks, 320 L3CacheParamsOpt = Some(HCCacheParameters( 321 name = "L3", 322 level = 3, 323 ways = ways, 324 sets = sets, 325 inclusive = inclusive, 326 clientCaches = tiles.map{ core => 327 val l2params = core.L2CacheParamsOpt.get.toCacheParams 328 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 329 }, 330 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 331 ctrl = Some(CacheCtrl( 332 address = 0x39000000, 333 numCores = tiles.size 334 )), 335 reqField = Seq(utility.ReqSourceField()), 336 sramClkDivBy2 = true, 337 sramDepthDiv = 4, 338 tagECC = Some("secded"), 339 dataECC = Some("secded"), 340 simulation = !site(DebugOptionsKey).FPGAPlatform, 341 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 342 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 343 )) 344 ) 345}) 346 347class WithL3DebugConfig extends Config( 348 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 349) 350 351class MinimalL3DebugConfig(n: Int = 1) extends Config( 352 new WithL3DebugConfig ++ new MinimalConfig(n) 353) 354 355class DefaultL3DebugConfig(n: Int = 1) extends Config( 356 new WithL3DebugConfig ++ new BaseConfig(n) 357) 358 359class WithFuzzer extends Config((site, here, up) => { 360 case DebugOptionsKey => up(DebugOptionsKey).copy( 361 EnablePerfDebug = false, 362 ) 363 case SoCParamsKey => up(SoCParamsKey).copy( 364 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 365 enablePerf = false, 366 )), 367 ) 368 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 369 p.copy( 370 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 371 enablePerf = false, 372 )), 373 ) 374 } 375}) 376 377class MinimalAliasDebugConfig(n: Int = 1) extends Config( 378 new WithNKBL3(512, inclusive = false) ++ 379 new WithNKBL2(256, inclusive = true) ++ 380 new WithNKBL1D(128) ++ 381 new MinimalConfig(n) 382) 383 384class MediumConfig(n: Int = 1) extends Config( 385 new WithNKBL3(4096, inclusive = false, banks = 4) 386 ++ new WithNKBL2(512, inclusive = true) 387 ++ new WithNKBL1D(128) 388 ++ new BaseConfig(n) 389) 390 391class FuzzConfig(dummy: Int = 0) extends Config( 392 new WithFuzzer 393 ++ new DefaultConfig(1) 394) 395 396class DefaultConfig(n: Int = 1) extends Config( 397 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 398 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 399 ++ new WithNKBL1D(64, ways = 8) 400 ++ new BaseConfig(n) 401) 402 403class WithCHI extends Config((_, _, _) => { 404 case EnableCHI => true 405}) 406 407class KunminghuV2Config(n: Int = 1) extends Config( 408 new WithCHI 409 ++ new Config((site, here, up) => { 410 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 411 }) 412 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 413 ++ new WithNKBL1D(64, ways = 8) 414 ++ new DefaultConfig(n) 415) 416 417class XSNoCTopConfig(n: Int = 1) extends Config( 418 (new KunminghuV2Config(n)).alter((site, here, up) => { 419 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 420 }) 421) 422 423class FpgaDefaultConfig(n: Int = 1) extends Config( 424 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 425 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 426 ++ new WithNKBL1D(64, ways = 8) 427 ++ new BaseConfig(n)).alter((site, here, up) => { 428 case DebugOptionsKey => up(DebugOptionsKey).copy( 429 AlwaysBasicDiff = false, 430 AlwaysBasicDB = false 431 ) 432 case SoCParamsKey => up(SoCParamsKey).copy( 433 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 434 sramClkDivBy2 = false, 435 )), 436 ) 437 }) 438) 439