1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 41 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 42 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 43 case JtagDTMKey => JtagDTMKey 44 case MaxHartIdBits => 2 45 case EnableJtag => false.B 46}) 47 48// Synthesizable minimal XiangShan 49// * It is still an out-of-order, super-scalaer arch 50// * L1 cache included 51// * L2 cache NOT included 52// * L3 cache included 53class MinimalConfig(n: Int = 1) extends Config( 54 new BaseConfig(n).alter((site, here, up) => { 55 case XSTileKey => up(XSTileKey).map( 56 _.copy( 57 DecodeWidth = 2, 58 RenameWidth = 2, 59 FetchWidth = 4, 60 IssQueSize = 8, 61 NRPhyRegs = 64, 62 LoadQueueSize = 16, 63 StoreQueueSize = 12, 64 RobSize = 32, 65 FtqSize = 8, 66 IBufSize = 16, 67 StoreBufferSize = 4, 68 StoreBufferThreshold = 3, 69 dpParams = DispatchParameters( 70 IntDqSize = 12, 71 FpDqSize = 12, 72 LsDqSize = 12, 73 IntDqDeqWidth = 4, 74 FpDqDeqWidth = 4, 75 LsDqDeqWidth = 4 76 ), 77 exuParameters = ExuParameters( 78 JmpCnt = 1, 79 AluCnt = 2, 80 MulCnt = 0, 81 MduCnt = 1, 82 FmacCnt = 1, 83 FmiscCnt = 1, 84 FmiscDivSqrtCnt = 0, 85 LduCnt = 2, 86 StuCnt = 2 87 ), 88 icacheParameters = ICacheParameters( 89 nSets = 64, // 16KB ICache 90 tagECC = Some("parity"), 91 dataECC = Some("parity"), 92 replacer = Some("setplru"), 93 nMissEntries = 2, 94 nReleaseEntries = 2 95 ), 96 dcacheParametersOpt = Some(DCacheParameters( 97 nSets = 64, // 32KB DCache 98 nWays = 8, 99 tagECC = Some("secded"), 100 dataECC = Some("secded"), 101 replacer = Some("setplru"), 102 nMissEntries = 4, 103 nProbeEntries = 4, 104 nReleaseEntries = 8, 105 )), 106 EnableBPD = false, // disable TAGE 107 EnableLoop = false, 108 itlbParameters = TLBParameters( 109 name = "itlb", 110 fetchi = true, 111 useDmode = false, 112 sameCycle = true, 113 normalReplacer = Some("plru"), 114 superReplacer = Some("plru"), 115 normalNWays = 4, 116 normalNSets = 1, 117 superNWays = 2, 118 shouldBlock = true 119 ), 120 ldtlbParameters = TLBParameters( 121 name = "ldtlb", 122 normalNSets = 4, // when da or sa 123 normalNWays = 1, // when fa or sa 124 normalAssociative = "sa", 125 normalReplacer = Some("setplru"), 126 superNWays = 4, 127 normalAsVictim = true, 128 outReplace = true 129 ), 130 sttlbParameters = TLBParameters( 131 name = "sttlb", 132 normalNSets = 4, // when da or sa 133 normalNWays = 1, // when fa or sa 134 normalAssociative = "sa", 135 normalReplacer = Some("setplru"), 136 normalAsVictim = true, 137 superNWays = 4, 138 outReplace = true 139 ), 140 btlbParameters = TLBParameters( 141 name = "btlb", 142 normalNSets = 1, 143 normalNWays = 8, 144 superNWays = 2 145 ), 146 l2tlbParameters = L2TLBParameters( 147 l1Size = 4, 148 l2nSets = 4, 149 l2nWays = 4, 150 l3nSets = 4, 151 l3nWays = 8, 152 spSize = 2, 153 ), 154 L2CacheParamsOpt = None // remove L2 Cache 155 ) 156 ) 157 case SoCParamsKey => up(SoCParamsKey).copy( 158 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 159 sets = 1024 160 )), 161 L3NBanks = 1 162 ) 163 }) 164) 165 166// Non-synthesizable MinimalConfig, for fast simulation only 167class MinimalSimConfig(n: Int = 1) extends Config( 168 new MinimalConfig(n).alter((site, here, up) => { 169 case XSTileKey => up(XSTileKey).map(_.copy( 170 dcacheParametersOpt = None, 171 softPTW = true 172 )) 173 case SoCParamsKey => up(SoCParamsKey).copy( 174 L3CacheParamsOpt = None 175 ) 176 }) 177) 178 179class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 180 case XSTileKey => 181 val sets = n * 1024 / ways / 64 182 up(XSTileKey).map(_.copy( 183 dcacheParametersOpt = Some(DCacheParameters( 184 nSets = sets, 185 nWays = ways, 186 tagECC = Some("secded"), 187 dataECC = Some("secded"), 188 replacer = Some("setplru"), 189 nMissEntries = 16, 190 nProbeEntries = 8, 191 nReleaseEntries = 18 192 )) 193 )) 194}) 195 196class WithNKBL2 197( 198 n: Int, 199 ways: Int = 8, 200 inclusive: Boolean = true, 201 banks: Int = 1, 202 alwaysReleaseData: Boolean = false 203) extends Config((site, here, up) => { 204 case XSTileKey => 205 val upParams = up(XSTileKey) 206 val l2sets = n * 1024 / banks / ways / 64 207 upParams.map(p => p.copy( 208 L2CacheParamsOpt = Some(HCCacheParameters( 209 name = "L2", 210 level = 2, 211 ways = ways, 212 sets = l2sets, 213 inclusive = inclusive, 214 alwaysReleaseData = alwaysReleaseData, 215 clientCaches = Seq(CacheParameters( 216 "dcache", 217 sets = 2 * p.dcacheParametersOpt.get.nSets, 218 ways = p.dcacheParametersOpt.get.nWays + 2, 219 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 220 )), 221 reqField = Seq(PreferCacheField()), 222 echoField = Seq(DirtyField()), 223 prefetch = Some(huancun.prefetch.BOPParameters()), 224 enablePerf = true 225 )), 226 L2NBanks = banks 227 )) 228}) 229 230class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 231 case SoCParamsKey => 232 val sets = n * 1024 / banks / ways / 64 233 val tiles = site(XSTileKey) 234 up(SoCParamsKey).copy( 235 L3NBanks = banks, 236 L3CacheParamsOpt = Some(HCCacheParameters( 237 name = "L3", 238 level = 3, 239 ways = ways, 240 sets = sets, 241 inclusive = inclusive, 242 clientCaches = tiles.map{ core => 243 val l2params = core.L2CacheParamsOpt.get.toCacheParams 244 l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways) 245 }, 246 enablePerf = true, 247 ctrl = Some(CacheCtrl( 248 address = 0x39000000, 249 numCores = tiles.size 250 )), 251 sramClkDivBy2 = true 252 )) 253 ) 254}) 255 256class WithL3DebugConfig extends Config( 257 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 258) 259 260class MinimalL3DebugConfig(n: Int = 1) extends Config( 261 new WithL3DebugConfig ++ new MinimalConfig(n) 262) 263 264class DefaultL3DebugConfig(n: Int = 1) extends Config( 265 new WithL3DebugConfig ++ new BaseConfig(n) 266) 267 268class MinimalAliasDebugConfig(n: Int = 1) extends Config( 269 new WithNKBL3(512, inclusive = false) ++ 270 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 271 new WithNKBL1D(128) ++ 272 new MinimalConfig(n) 273) 274 275class MediumConfig(n: Int = 1) extends Config( 276 new WithNKBL3(4096, inclusive = false, banks = 4) 277 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 278 ++ new WithNKBL1D(128) 279 ++ new BaseConfig(n) 280) 281 282class DefaultConfig(n: Int = 1) extends Config( 283 new WithNKBL3(8 * 1024, inclusive = false, banks = 4, ways = 8) 284 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 285 ++ new WithNKBL1D(128) 286 ++ new BaseConfig(n) 287) 288