xref: /XiangShan/src/main/scala/top/Configs.scala (revision 066ac8a465b27b54ba22458ff1a67bcd28215d73) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import system._
24import chipsalliance.rocketchip.config._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
26import xiangshan.frontend.ICacheParameters
27import freechips.rocketchip.devices.debug._
28import freechips.rocketchip.tile.MaxHartIdBits
29import xiangshan.backend.dispatch.DispatchParameters
30import xiangshan.backend.exu.ExuParameters
31import xiangshan.cache.DCacheParameters
32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
33import device.{EnableJtag, XSDebugModuleParams}
34import huancun._
35
36class BaseConfig(n: Int) extends Config((site, here, up) => {
37  case XLen => 64
38  case DebugOptionsKey => DebugOptions()
39  case SoCParamsKey => SoCParameters()
40  case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
41  case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
42  case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
43  case JtagDTMKey => JtagDTMKey
44  case MaxHartIdBits => 2
45  case EnableJtag => false.B
46})
47
48// Synthesizable minimal XiangShan
49// * It is still an out-of-order, super-scalaer arch
50// * L1 cache included
51// * L2 cache NOT included
52// * L3 cache included
53class MinimalConfig(n: Int = 1) extends Config(
54  new BaseConfig(n).alter((site, here, up) => {
55    case XSTileKey => up(XSTileKey).map(
56      _.copy(
57        DecodeWidth = 2,
58        RenameWidth = 2,
59        FetchWidth = 4,
60        IssQueSize = 8,
61        NRPhyRegs = 64,
62        LoadQueueSize = 16,
63        StoreQueueSize = 12,
64        RobSize = 32,
65        FtqSize = 8,
66        IBufSize = 16,
67        StoreBufferSize = 4,
68        StoreBufferThreshold = 3,
69        dpParams = DispatchParameters(
70          IntDqSize = 12,
71          FpDqSize = 12,
72          LsDqSize = 12,
73          IntDqDeqWidth = 4,
74          FpDqDeqWidth = 4,
75          LsDqDeqWidth = 4
76        ),
77        exuParameters = ExuParameters(
78          JmpCnt = 1,
79          AluCnt = 2,
80          MulCnt = 0,
81          MduCnt = 1,
82          FmacCnt = 1,
83          FmiscCnt = 1,
84          FmiscDivSqrtCnt = 0,
85          LduCnt = 2,
86          StuCnt = 2
87        ),
88        icacheParameters = ICacheParameters(
89          nSets = 64, // 16KB ICache
90          tagECC = Some("parity"),
91          dataECC = Some("parity"),
92          replacer = Some("setplru"),
93          nMissEntries = 2
94        ),
95        dcacheParametersOpt = Some(DCacheParameters(
96          nSets = 64, // 32KB DCache
97          nWays = 8,
98          tagECC = Some("secded"),
99          dataECC = Some("secded"),
100          replacer = Some("setplru"),
101          nMissEntries = 4,
102          nProbeEntries = 4,
103          nReleaseEntries = 8,
104        )),
105        EnableBPD = false, // disable TAGE
106        EnableLoop = false,
107        itlbParameters = TLBParameters(
108          name = "itlb",
109          fetchi = true,
110          useDmode = false,
111          sameCycle = true,
112          normalReplacer = Some("plru"),
113          superReplacer = Some("plru"),
114          normalNWays = 4,
115          normalNSets = 1,
116          superNWays = 2,
117          shouldBlock = true
118        ),
119        ldtlbParameters = TLBParameters(
120          name = "ldtlb",
121          normalNSets = 4, // when da or sa
122          normalNWays = 1, // when fa or sa
123          normalAssociative = "sa",
124          normalReplacer = Some("setplru"),
125          superNWays = 4,
126          normalAsVictim = true,
127          outReplace = true
128        ),
129        sttlbParameters = TLBParameters(
130          name = "sttlb",
131          normalNSets = 4, // when da or sa
132          normalNWays = 1, // when fa or sa
133          normalAssociative = "sa",
134          normalReplacer = Some("setplru"),
135          normalAsVictim = true,
136          superNWays = 4,
137          outReplace = true
138        ),
139        btlbParameters = TLBParameters(
140          name = "btlb",
141          normalNSets = 1,
142          normalNWays = 8,
143          superNWays = 2
144        ),
145        l2tlbParameters = L2TLBParameters(
146          l1Size = 4,
147          l2nSets = 4,
148          l2nWays = 4,
149          l3nSets = 4,
150          l3nWays = 8,
151          spSize = 2,
152        ),
153        L2CacheParamsOpt = None // remove L2 Cache
154      )
155    )
156    case SoCParamsKey => up(SoCParamsKey).copy(
157      L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
158        sets = 1024
159      )),
160      L3NBanks = 1
161    )
162  })
163)
164
165// Non-synthesizable MinimalConfig, for fast simulation only
166class MinimalSimConfig(n: Int = 1) extends Config(
167  new MinimalConfig(n).alter((site, here, up) => {
168    case XSTileKey => up(XSTileKey).map(_.copy(
169      dcacheParametersOpt = None,
170      softPTW = true
171    ))
172    case SoCParamsKey => up(SoCParamsKey).copy(
173      L3CacheParamsOpt = None
174    )
175  })
176)
177
178class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
179  case XSTileKey =>
180    val sets = n * 1024 / ways / 64
181    up(XSTileKey).map(_.copy(
182      dcacheParametersOpt = Some(DCacheParameters(
183        nSets = sets,
184        nWays = ways,
185        tagECC = Some("secded"),
186        dataECC = Some("secded"),
187        replacer = Some("setplru"),
188        nMissEntries = 16,
189        nProbeEntries = 8,
190        nReleaseEntries = 18
191      ))
192    ))
193})
194
195class WithNKBL2
196(
197  n: Int,
198  ways: Int = 8,
199  inclusive: Boolean = true,
200  banks: Int = 1,
201  alwaysReleaseData: Boolean = false
202) extends Config((site, here, up) => {
203  case XSTileKey =>
204    val upParams = up(XSTileKey)
205    val l2sets = n * 1024 / banks / ways / 64
206    upParams.map(p => p.copy(
207      L2CacheParamsOpt = Some(HCCacheParameters(
208        name = "L2",
209        level = 2,
210        ways = ways,
211        sets = l2sets,
212        inclusive = inclusive,
213        alwaysReleaseData = alwaysReleaseData,
214        clientCaches = Seq(CacheParameters(
215          "dcache",
216          sets = 2 * p.dcacheParametersOpt.get.nSets,
217          ways = p.dcacheParametersOpt.get.nWays + 2,
218          aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
219        )),
220        reqField = Seq(PreferCacheField()),
221        echoField = Seq(DirtyField()),
222        prefetch = Some(huancun.prefetch.BOPParameters()),
223        enablePerf = true
224      )),
225      L2NBanks = banks
226    ))
227})
228
229class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
230  case SoCParamsKey =>
231    val sets = n * 1024 / banks / ways / 64
232    val tiles = site(XSTileKey)
233    up(SoCParamsKey).copy(
234      L3NBanks = banks,
235      L3CacheParamsOpt = Some(HCCacheParameters(
236        name = "L3",
237        level = 3,
238        ways = ways,
239        sets = sets,
240        inclusive = inclusive,
241        clientCaches = tiles.map{ core =>
242          val l2params = core.L2CacheParamsOpt.get.toCacheParams
243          l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways)
244        },
245        enablePerf = true,
246        ctrl = Some(CacheCtrl(
247          address = 0x39000000,
248          numCores = tiles.size
249        ))
250      ))
251    )
252})
253
254class WithL3DebugConfig extends Config(
255  new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
256)
257
258class MinimalL3DebugConfig(n: Int = 1) extends Config(
259  new WithL3DebugConfig ++ new MinimalConfig(n)
260)
261
262class DefaultL3DebugConfig(n: Int = 1) extends Config(
263  new WithL3DebugConfig ++ new BaseConfig(n)
264)
265
266class MinimalAliasDebugConfig(n: Int = 1) extends Config(
267  new WithNKBL3(512, inclusive = false) ++
268    new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++
269    new WithNKBL1D(128) ++
270    new MinimalConfig(n)
271)
272
273class MediumConfig(n: Int = 1) extends Config(
274  new WithNKBL3(4096, inclusive = false, banks = 4)
275    ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true)
276    ++ new WithNKBL1D(128)
277    ++ new BaseConfig(n)
278)
279
280class DefaultConfig(n: Int = 1) extends Config(
281  new WithNKBL3(8 * 1024, inclusive = false, banks = 4, ways = 8)
282    ++ new WithNKBL2(2 * 512, inclusive = false, banks = 2, alwaysReleaseData = true)
283    ++ new WithNKBL1D(128)
284    ++ new BaseConfig(n)
285)
286