1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import coupledL2.prefetch._ 43import xiangshan.frontend.icache.ICacheParameters 44 45class BaseConfig(n: Int) extends Config((site, here, up) => { 46 case XLen => 64 47 case DebugOptionsKey => DebugOptions() 48 case SoCParamsKey => SoCParameters() 49 case PMParameKey => PMParameters() 50 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 51 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 52 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 53 case JtagDTMKey => JtagDTMKey 54 case MaxHartIdBits => log2Up(n) max 6 55 case EnableJtag => true.B 56}) 57 58// Synthesizable minimal XiangShan 59// * It is still an out-of-order, super-scalaer arch 60// * L1 cache included 61// * L2 cache NOT included 62// * L3 cache included 63class MinimalConfig(n: Int = 1) extends Config( 64 new BaseConfig(n).alter((site, here, up) => { 65 case XSTileKey => up(XSTileKey).map( 66 p => p.copy( 67 DecodeWidth = 6, 68 RenameWidth = 6, 69 RobCommitWidth = 8, 70 FetchWidth = 4, 71 VirtualLoadQueueSize = 24, 72 LoadQueueRARSize = 24, 73 LoadQueueRAWSize = 12, 74 LoadQueueReplaySize = 24, 75 LoadUncacheBufferSize = 8, 76 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 77 RollbackGroupSize = 8, 78 StoreQueueSize = 20, 79 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 80 StoreQueueForwardWithMask = true, 81 // ============ VLSU ============ 82 VlMergeBufferSize = 8, 83 VsMergeBufferSize = 8, 84 UopWritebackWidth = 2, 85 SplitBufferSize = 8, 86 // ============================== 87 RobSize = 48, 88 RabSize = 96, 89 FtqSize = 8, 90 IBufSize = 24, 91 IBufNBank = 6, 92 StoreBufferSize = 4, 93 StoreBufferThreshold = 3, 94 IssueQueueSize = 10, 95 IssueQueueCompEntrySize = 4, 96 dpParams = DispatchParameters( 97 IntDqSize = 12, 98 FpDqSize = 12, 99 LsDqSize = 12, 100 IntDqDeqWidth = 8, 101 FpDqDeqWidth = 6, 102 VecDqDeqWidth = 6, 103 LsDqDeqWidth = 6 104 ), 105 intPreg = IntPregParams( 106 numEntries = 64, 107 numRead = None, 108 numWrite = None, 109 ), 110 vfPreg = VfPregParams( 111 numEntries = 160, 112 numRead = None, 113 numWrite = None, 114 ), 115 icacheParameters = ICacheParameters( 116 nSets = 64, // 16KB ICache 117 tagECC = Some("parity"), 118 dataECC = Some("parity"), 119 replacer = Some("setplru"), 120 nMissEntries = 2, 121 nReleaseEntries = 1, 122 nProbeEntries = 2, 123 // fdip 124 enableICachePrefetch = true, 125 prefetchToL1 = false, 126 ), 127 dcacheParametersOpt = Some(DCacheParameters( 128 nSets = 64, // 32KB DCache 129 nWays = 8, 130 tagECC = Some("secded"), 131 dataECC = Some("secded"), 132 replacer = Some("setplru"), 133 nMissEntries = 4, 134 nProbeEntries = 4, 135 nReleaseEntries = 8, 136 nMaxPrefetchEntry = 2, 137 )), 138 // ============ BPU =============== 139 EnableLoop = false, 140 EnableGHistDiff = false, 141 FtbSize = 256, 142 FtbWays = 2, 143 RasSize = 8, 144 RasSpecSize = 16, 145 TageTableInfos = 146 Seq((512, 4, 6), 147 (512, 9, 6), 148 (1024, 19, 6)), 149 SCNRows = 128, 150 SCNTables = 2, 151 SCHistLens = Seq(0, 5), 152 ITTageTableInfos = 153 Seq((256, 4, 7), 154 (256, 8, 7), 155 (512, 16, 7)), 156 // ================================ 157 itlbParameters = TLBParameters( 158 name = "itlb", 159 fetchi = true, 160 useDmode = false, 161 NWays = 4, 162 ), 163 ldtlbParameters = TLBParameters( 164 name = "ldtlb", 165 NWays = 4, 166 partialStaticPMP = true, 167 outsideRecvFlush = true, 168 outReplace = false, 169 lgMaxSize = 4 170 ), 171 sttlbParameters = TLBParameters( 172 name = "sttlb", 173 NWays = 4, 174 partialStaticPMP = true, 175 outsideRecvFlush = true, 176 outReplace = false, 177 lgMaxSize = 4 178 ), 179 hytlbParameters = TLBParameters( 180 name = "hytlb", 181 NWays = 4, 182 partialStaticPMP = true, 183 outsideRecvFlush = true, 184 outReplace = false, 185 lgMaxSize = 4 186 ), 187 pftlbParameters = TLBParameters( 188 name = "pftlb", 189 NWays = 4, 190 partialStaticPMP = true, 191 outsideRecvFlush = true, 192 outReplace = false, 193 lgMaxSize = 4 194 ), 195 btlbParameters = TLBParameters( 196 name = "btlb", 197 NWays = 4, 198 ), 199 l2tlbParameters = L2TLBParameters( 200 l1Size = 4, 201 l2nSets = 4, 202 l2nWays = 4, 203 l3nSets = 4, 204 l3nWays = 8, 205 spSize = 2, 206 ), 207 L2CacheParamsOpt = Some(L2Param( 208 name = "L2", 209 ways = 8, 210 sets = 128, 211 echoField = Seq(huancun.DirtyField()), 212 prefetch = Nil, 213 clientCaches = Seq(L1Param( 214 "dcache", 215 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 216 )), 217 )), 218 L2NBanks = 2, 219 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 220 ) 221 ) 222 case SoCParamsKey => 223 val tiles = site(XSTileKey) 224 up(SoCParamsKey).copy( 225 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 226 sets = 1024, 227 inclusive = false, 228 clientCaches = tiles.map{ core => 229 val clientDirBytes = tiles.map{ t => 230 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 231 }.sum 232 val l2params = core.L2CacheParamsOpt.get.toCacheParams 233 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 234 }, 235 simulation = !site(DebugOptionsKey).FPGAPlatform, 236 prefetch = None 237 )), 238 L3NBanks = 1 239 ) 240 }) 241) 242 243// Non-synthesizable MinimalConfig, for fast simulation only 244class MinimalSimConfig(n: Int = 1) extends Config( 245 new MinimalConfig(n).alter((site, here, up) => { 246 case XSTileKey => up(XSTileKey).map(_.copy( 247 dcacheParametersOpt = None, 248 softPTW = true 249 )) 250 case SoCParamsKey => up(SoCParamsKey).copy( 251 L3CacheParamsOpt = None 252 ) 253 }) 254) 255 256class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 257 case XSTileKey => 258 val sets = n * 1024 / ways / 64 259 up(XSTileKey).map(_.copy( 260 dcacheParametersOpt = Some(DCacheParameters( 261 nSets = sets, 262 nWays = ways, 263 tagECC = Some("secded"), 264 dataECC = Some("secded"), 265 replacer = Some("setplru"), 266 nMissEntries = 16, 267 nProbeEntries = 8, 268 nReleaseEntries = 18, 269 nMaxPrefetchEntry = 6, 270 )) 271 )) 272}) 273 274class WithNKBL2 275( 276 n: Int, 277 ways: Int = 8, 278 inclusive: Boolean = true, 279 banks: Int = 1, 280 tp: Boolean = true 281) extends Config((site, here, up) => { 282 case XSTileKey => 283 require(inclusive, "L2 must be inclusive") 284 val upParams = up(XSTileKey) 285 val l2sets = n * 1024 / banks / ways / 64 286 upParams.map(p => p.copy( 287 L2CacheParamsOpt = Some(L2Param( 288 name = "L2", 289 ways = ways, 290 sets = l2sets, 291 clientCaches = Seq(L1Param( 292 "dcache", 293 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 294 ways = p.dcacheParametersOpt.get.nWays + 2, 295 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 296 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 297 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 298 )), 299 reqField = Seq(utility.ReqSourceField()), 300 echoField = Seq(huancun.DirtyField()), 301 prefetch = Seq(PrefetchReceiverParams(), BOPParameters()) ++ (if (tp) Seq(TPParameters()) else Nil), 302 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 303 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 304 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 305 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 306 )), 307 L2NBanks = banks 308 )) 309}) 310 311class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 312 case SoCParamsKey => 313 val sets = n * 1024 / banks / ways / 64 314 val tiles = site(XSTileKey) 315 val clientDirBytes = tiles.map{ t => 316 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 317 }.sum 318 up(SoCParamsKey).copy( 319 L3NBanks = banks, 320 L3CacheParamsOpt = Some(HCCacheParameters( 321 name = "L3", 322 level = 3, 323 ways = ways, 324 sets = sets, 325 inclusive = inclusive, 326 clientCaches = tiles.map{ core => 327 val l2params = core.L2CacheParamsOpt.get.toCacheParams 328 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 329 }, 330 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 331 ctrl = Some(CacheCtrl( 332 address = 0x39000000, 333 numCores = tiles.size 334 )), 335 reqField = Seq(utility.ReqSourceField()), 336 sramClkDivBy2 = true, 337 sramDepthDiv = 4, 338 tagECC = Some("secded"), 339 dataECC = Some("secded"), 340 simulation = !site(DebugOptionsKey).FPGAPlatform, 341 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 342 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 343 )) 344 ) 345}) 346 347class WithL3DebugConfig extends Config( 348 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 349) 350 351class MinimalL3DebugConfig(n: Int = 1) extends Config( 352 new WithL3DebugConfig ++ new MinimalConfig(n) 353) 354 355class DefaultL3DebugConfig(n: Int = 1) extends Config( 356 new WithL3DebugConfig ++ new BaseConfig(n) 357) 358 359class WithFuzzer extends Config((site, here, up) => { 360 case DebugOptionsKey => up(DebugOptionsKey).copy( 361 EnablePerfDebug = false, 362 ) 363 case SoCParamsKey => up(SoCParamsKey).copy( 364 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 365 enablePerf = false, 366 )), 367 ) 368 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 369 p.copy( 370 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 371 enablePerf = false, 372 )), 373 ) 374 } 375}) 376 377class MinimalAliasDebugConfig(n: Int = 1) extends Config( 378 new WithNKBL3(512, inclusive = false) ++ 379 new WithNKBL2(256, inclusive = true) ++ 380 new WithNKBL1D(128) ++ 381 new MinimalConfig(n) 382) 383 384class MediumConfig(n: Int = 1) extends Config( 385 new WithNKBL3(4096, inclusive = false, banks = 4) 386 ++ new WithNKBL2(512, inclusive = true) 387 ++ new WithNKBL1D(128) 388 ++ new BaseConfig(n) 389) 390 391class FuzzConfig(dummy: Int = 0) extends Config( 392 new WithFuzzer 393 ++ new DefaultConfig(1) 394) 395 396class DefaultConfig(n: Int = 1) extends Config( 397 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 398 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 399 ++ new WithNKBL1D(64, ways = 8) 400 ++ new BaseConfig(n) 401) 402 403class WithCHI extends Config((_, _, _) => { 404 case EnableCHI => true 405}) 406 407class KunminghuV2Config(n: Int = 1) extends Config( 408 new WithCHI 409 ++ new Config((site, here, up) => { 410 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 411 }) 412 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 413 ++ new WithNKBL1D(64, ways = 8) 414 ++ new BaseConfig(n) 415)