xref: /XiangShan/src/main/scala/system/SoC.scala (revision e76e9e542aac8b8f337b85668aaec6ed881b6a28) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.PMAConst
35import xiangshan.{DebugOptionsKey, XSTileKey}
36import coupledL2.EnableCHI
37import coupledL2.tl2chi.CHIIssue
38import xiangshan.PMParameKey
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44  EnableILA: Boolean = false,
45  PAddrBits: Int = 48,
46  PmemRanges: Seq[(BigInt, BigInt)] = Seq((0x80000000L, 0x80000000000L)),
47  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
48  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
49  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
50  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
51  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
52  extIntrs: Int = 64,
53  L3NBanks: Int = 4,
54  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
55    name = "L3",
56    level = 3,
57    ways = 8,
58    sets = 2048 // 1MB per bank
59  )),
60  XSTopPrefix: Option[String] = None,
61  NodeIDWidthList: Map[String, Int] = Map(
62    "B" -> 7,
63    "E.b" -> 11
64  ),
65  NumHart: Int = 64,
66  NumIRFiles: Int = 7,
67  NumIRSrc: Int = 256,
68  UseXSNoCTop: Boolean = false,
69  IMSICUseTL: Boolean = false,
70  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 4, sync = 3, safe = false)),
71  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
72){
73  // L3 configurations
74  val L3InnerBusWidth = 256
75  val L3BlockSize = 64
76  // on chip network configurations
77  val L3OuterBusWidth = 256
78  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
79}
80
81trait HasSoCParameter {
82  implicit val p: Parameters
83
84  val soc = p(SoCParamsKey)
85  val debugOpts = p(DebugOptionsKey)
86  val tiles = p(XSTileKey)
87  val enableCHI = p(EnableCHI)
88  val issue = p(CHIIssue)
89
90  val NumCores = tiles.size
91  val EnableILA = soc.EnableILA
92
93  // L3 configurations
94  val L3InnerBusWidth = soc.L3InnerBusWidth
95  val L3BlockSize = soc.L3BlockSize
96  val L3NBanks = soc.L3NBanks
97
98  // on chip network configurations
99  val L3OuterBusWidth = soc.L3OuterBusWidth
100
101  val NrExtIntr = soc.extIntrs
102
103  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
104
105  val NumIRSrc = soc.NumIRSrc
106
107  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
108    soc.EnableCHIAsyncBridge else None
109  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
110}
111
112trait HasPeripheralRanges {
113  implicit val p: Parameters
114
115  private def soc = p(SoCParamsKey)
116  private def dm = p(DebugModuleKey)
117  private def pmParams = p(PMParameKey)
118
119  private def mmpma = pmParams.mmpma
120
121  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
122    "CLINT" -> soc.CLINTRange,
123    "BEU"   -> soc.BEURange,
124    "PLIC"  -> soc.PLICRange,
125    "PLL"   -> soc.PLLRange,
126    "UART"  -> soc.UARTLiteRange,
127    "DEBUG" -> dm.get.address,
128    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
129  ) ++ (
130    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
131      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
132    else
133      Map()
134  )
135
136  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
137    acc.flatMap(_.subtract(x))
138  }
139}
140
141class ILABundle extends Bundle {}
142
143
144abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
145  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
146  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
147  val l3_xbar = Option.when(!enableCHI)(TLXbar())
148  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
149
150  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
151}
152
153// We adapt the following three traits from rocket-chip.
154// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
155trait HaveSlaveAXI4Port {
156  this: BaseSoC =>
157
158  val idBits = 14
159
160  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
161    Seq(AXI4MasterParameters(
162      name = "dma",
163      id = IdRange(0, 1 << idBits)
164    ))
165  )))
166
167  if (l3_xbar.isDefined) {
168    val errorDevice = LazyModule(new TLError(
169      params = DevNullParams(
170        address = Seq(AddressSet(0x0, 0x7fffffffL)),
171        maxAtomic = 8,
172        maxTransfer = 64),
173      beatBytes = L3InnerBusWidth / 8
174    ))
175    errorDevice.node :=
176      l3_xbar.get :=
177      TLFIFOFixer() :=
178      TLWidthWidget(32) :=
179      AXI4ToTL() :=
180      AXI4UserYanker(Some(1)) :=
181      AXI4Fragmenter() :=
182      AXI4Buffer() :=
183      AXI4Buffer() :=
184      AXI4IdIndexer(1) :=
185      l3FrontendAXI4Node
186  }
187
188  val dma = InModuleBody {
189    l3FrontendAXI4Node.makeIOs()
190  }
191}
192
193trait HaveAXI4MemPort {
194  this: BaseSoC =>
195  val device = new MemoryDevice
196  // 48-bit physical address
197  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
198  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
199    AXI4SlavePortParameters(
200      slaves = Seq(
201        AXI4SlaveParameters(
202          address = memRange,
203          regionType = RegionType.UNCACHED,
204          executable = true,
205          supportsRead = TransferSizes(1, L3BlockSize),
206          supportsWrite = TransferSizes(1, L3BlockSize),
207          interleavedId = Some(0),
208          resources = device.reg("mem")
209        )
210      ),
211      beatBytes = L3OuterBusWidth / 8,
212      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
213    )
214  ))
215
216  val mem_xbar = TLXbar()
217  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
218  val axi4mem_node = AXI4IdentityNode()
219
220  if (enableCHI) {
221    axi4mem_node :=
222      soc_xbar.get
223  } else {
224    mem_xbar :=*
225      TLBuffer.chainNode(2) :=
226      TLCacheCork() :=
227      l3_mem_pmu :=
228      TLClientsMerger() :=
229      TLXbar() :=*
230      bankedNode.get
231
232    mem_xbar :=
233      TLWidthWidget(8) :=
234      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
235      peripheralXbar.get
236
237    axi4mem_node :=
238      TLToAXI4() :=
239      TLSourceShrinker(64) :=
240      TLWidthWidget(L3OuterBusWidth / 8) :=
241      TLBuffer.chainNode(2) :=
242      mem_xbar
243  }
244
245  memAXI4SlaveNode :=
246    AXI4Buffer() :=
247    AXI4Buffer() :=
248    AXI4Buffer() :=
249    AXI4IdIndexer(idBits = 14) :=
250    AXI4UserYanker() :=
251    AXI4Deinterleaver(L3BlockSize) :=
252    axi4mem_node
253
254  val memory = InModuleBody {
255    memAXI4SlaveNode.makeIOs()
256  }
257}
258
259trait HaveAXI4PeripheralPort { this: BaseSoC =>
260  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
261  val uartParams = AXI4SlaveParameters(
262    address = Seq(soc.UARTLiteRange),
263    regionType = RegionType.UNCACHED,
264    supportsRead = TransferSizes(1, 32),
265    supportsWrite = TransferSizes(1, 32),
266    resources = uartDevice.reg
267  )
268  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
269    Seq(AXI4SlaveParameters(
270      address = peripheralRange,
271      regionType = RegionType.UNCACHED,
272      supportsRead = TransferSizes(1, 32),
273      supportsWrite = TransferSizes(1, 32),
274      interleavedId = Some(0)
275    ), uartParams),
276    beatBytes = 8
277  )))
278
279  val axi4peripheral_node = AXI4IdentityNode()
280  val error_xbar = Option.when(enableCHI)(TLXbar())
281
282  peripheralNode :=
283    AXI4UserYanker() :=
284    AXI4IdIndexer(idBits = 2) :=
285    AXI4Buffer() :=
286    AXI4Buffer() :=
287    AXI4Buffer() :=
288    AXI4Buffer() :=
289    AXI4UserYanker() :=
290    // AXI4Deinterleaver(8) :=
291    axi4peripheral_node
292
293  if (enableCHI) {
294    val error = LazyModule(new TLError(
295      params = DevNullParams(
296        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
297        maxAtomic = 8,
298        maxTransfer = 64),
299      beatBytes = 8
300    ))
301    error.node := error_xbar.get
302    axi4peripheral_node :=
303      AXI4Deinterleaver(8) :=
304      TLToAXI4() :=
305      error_xbar.get :=
306      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
307      TLFIFOFixer() :=
308      TLWidthWidget(L3OuterBusWidth / 8) :=
309      AXI4ToTL() :=
310      AXI4UserYanker() :=
311      soc_xbar.get
312  } else {
313    axi4peripheral_node :=
314      AXI4Deinterleaver(8) :=
315      TLToAXI4() :=
316      TLBuffer.chainNode(3) :=
317      peripheralXbar.get
318  }
319
320  val peripheral = InModuleBody {
321    peripheralNode.makeIOs()
322  }
323
324}
325
326class MemMisc()(implicit p: Parameters) extends BaseSoC
327  with HaveAXI4MemPort
328  with PMAConst
329  with HaveAXI4PeripheralPort
330{
331
332  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
333  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
334
335  val l3_in = TLTempNode()
336  val l3_out = TLTempNode()
337
338  val device_xbar = Option.when(enableCHI)(TLXbar())
339  device_xbar.foreach(_ := error_xbar.get)
340
341  if (l3_banked_xbar.isDefined) {
342    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
343    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
344  }
345  bankedNode match {
346    case Some(bankBinder) =>
347      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
348    case None =>
349  }
350
351  if(soc.L3CacheParamsOpt.isEmpty){
352    l3_out :*= l3_in
353  }
354
355  if (!enableCHI) {
356    for (port <- peripheral_ports.get) {
357      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
358    }
359  }
360
361  core_to_l3_ports.foreach { case _ =>
362    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
363      l3_banked_xbar.get :=*
364        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
365        TLBuffer() :=
366        core_out
367    }
368  }
369
370  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
371  if (enableCHI) { clint.node := device_xbar.get }
372  else { clint.node := peripheralXbar.get }
373
374  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
375    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
376    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
377      val in = IO(Input(Vec(num, Bool())))
378      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
379    }
380    lazy val module = new IntSourceNodeToModuleImp(this)
381  }
382
383  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
384  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
385
386  plic.intnode := plicSource.sourceNode
387  if (enableCHI) { plic.node := device_xbar.get }
388  else { plic.node := peripheralXbar.get }
389
390  val pll_node = TLRegisterNode(
391    address = Seq(soc.PLLRange),
392    device = new SimpleDevice("pll_ctrl", Seq()),
393    beatBytes = 8,
394    concurrency = 1
395  )
396  if (enableCHI) { pll_node := device_xbar.get }
397  else { pll_node := peripheralXbar.get }
398
399  val debugModule = LazyModule(new DebugModule(NumCores)(p))
400  if (enableCHI) {
401    debugModule.debug.node := device_xbar.get
402    // TODO: l3_xbar
403    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
404      error_xbar.get := sb2tl.node
405    }
406  } else {
407    debugModule.debug.node := peripheralXbar.get
408    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
409      l3_xbar.get := TLBuffer() := sb2tl.node
410    }
411  }
412
413  val pma = LazyModule(new TLPMA)
414  if (enableCHI) {
415    pma.node := TLBuffer.chainNode(4) := device_xbar.get
416  } else {
417    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
418  }
419
420  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
421
422    val debug_module_io = IO(new debugModule.DebugModuleIO)
423    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
424    val rtc_clock = IO(Input(Bool()))
425    val pll0_lock = IO(Input(Bool()))
426    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
427    val cacheable_check = IO(new TLPMAIO)
428    val clintTime = IO(Output(ValidIO(UInt(64.W))))
429
430    debugModule.module.io <> debug_module_io
431
432    // sync external interrupts
433    require(plicSource.module.in.length == ext_intrs.getWidth)
434    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
435      val ext_intr_sync = RegInit(0.U(3.W))
436      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
437      plic_in := ext_intr_sync(2)
438    }
439
440    pma.module.io <> cacheable_check
441
442    // positive edge sampling of the lower-speed rtc_clock
443    val rtcTick = RegInit(0.U(3.W))
444    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
445    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
446
447    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
448    val pll_lock = RegNext(next = pll0_lock, init = false.B)
449
450    clintTime := clint.module.io.time
451
452    pll0_ctrl <> VecInit(pll_ctrl_regs)
453
454    pll_node.regmap(
455      0x000 -> RegFieldGroup(
456        "Pll", Some("PLL ctrl regs"),
457        pll_ctrl_regs.zipWithIndex.map{
458          case (r, i) => RegField(32, r, RegFieldDesc(
459            s"PLL_ctrl_$i",
460            desc = s"PLL ctrl register #$i"
461          ))
462        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
463          "PLL_lock",
464          "PLL lock register"
465        ))
466      )
467    )
468  }
469
470  lazy val module = new SoCMiscImp(this)
471}
472
473class SoCMisc()(implicit p: Parameters) extends MemMisc
474  with HaveSlaveAXI4Port
475
476