1package system 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters} 7import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors} 8 9case object SoCParamsKey extends Field[SoCParameters] 10 11case class SoCParameters 12( 13 cores: List[XSCoreParameters], 14 EnableILA: Boolean = false, 15 extIntrs: Int = 150 16){ 17 val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y) 18 // L3 configurations 19 val useFakeL3Cache = false 20 val L3InnerBusWidth = 256 21 val L3Size = 4 * 1024 * 1024 // 4MB 22 val L3BlockSize = 64 23 val L3NBanks = 4 24 val L3NWays = 8 25 26 // on chip network configurations 27 val L3OuterBusWidth = 256 28 29} 30 31trait HasSoCParameter { 32 implicit val p: Parameters 33 34 val soc = p(SoCParamsKey) 35 val debugOpts = p(DebugOptionsKey) 36 val NumCores = soc.cores.size 37 val EnableILA = soc.EnableILA 38 39 // L3 configurations 40 val useFakeL3Cache = soc.useFakeL3Cache 41 val L3InnerBusWidth = soc.L3InnerBusWidth 42 val L3Size = soc.L3Size 43 val L3BlockSize = soc.L3BlockSize 44 val L3NBanks = soc.L3NBanks 45 val L3NWays = soc.L3NWays 46 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 47 48 // on chip network configurations 49 val L3OuterBusWidth = soc.L3OuterBusWidth 50 51 val NrExtIntr = soc.extIntrs 52} 53 54class ILABundle extends Bundle {} 55 56 57class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 58 val paddr = Valid(UInt(soc.PAddrBits.W)) 59 // for now, we only detect ecc 60 val ecc_error = Valid(Bool()) 61} 62 63class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors { 64 val icache = Vec(nCores, new L1CacheErrorInfo) 65 val l1plus = Vec(nCores, new L1CacheErrorInfo) 66 val dcache = Vec(nCores, new L1CacheErrorInfo) 67 68 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 69 List.tabulate(nCores){i => 70 List( 71 Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"), 72 Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"), 73 Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"), 74 Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"), 75 Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"), 76 Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error") 77 ) 78 }.flatten 79} 80