xref: /XiangShan/src/main/scala/system/SoC.scala (revision bb2f3f51dd67f6e16e0cc1ffe43368c9fc7e4aef) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import huancun._
30import top.BusPerfMonitor
31import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
32import xiangshan.backend.fu.PMAConst
33import xiangshan.{DebugOptionsKey, XSTileKey}
34import coupledL2.EnableCHI
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "L3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  )),
50  XSTopPrefix: Option[String] = None,
51  NodeIDWidth: Int = 7,
52  UseXSNoCTop: Boolean = false,
53  IMSICUseTL: Boolean = false
54){
55  // L3 configurations
56  val L3InnerBusWidth = 256
57  val L3BlockSize = 64
58  // on chip network configurations
59  val L3OuterBusWidth = 256
60}
61
62trait HasSoCParameter {
63  implicit val p: Parameters
64
65  val soc = p(SoCParamsKey)
66  val debugOpts = p(DebugOptionsKey)
67  val tiles = p(XSTileKey)
68  val enableCHI = p(EnableCHI)
69
70  val NumCores = tiles.size
71  val EnableILA = soc.EnableILA
72
73  // L3 configurations
74  val L3InnerBusWidth = soc.L3InnerBusWidth
75  val L3BlockSize = soc.L3BlockSize
76  val L3NBanks = soc.L3NBanks
77
78  // on chip network configurations
79  val L3OuterBusWidth = soc.L3OuterBusWidth
80
81  val NrExtIntr = soc.extIntrs
82}
83
84class ILABundle extends Bundle {}
85
86
87abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
88  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
89  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
90  val l3_xbar = Option.when(!enableCHI)(TLXbar())
91  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
92
93  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
94}
95
96// We adapt the following three traits from rocket-chip.
97// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
98trait HaveSlaveAXI4Port {
99  this: BaseSoC =>
100
101  val idBits = 14
102
103  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
104    Seq(AXI4MasterParameters(
105      name = "dma",
106      id = IdRange(0, 1 << idBits)
107    ))
108  )))
109
110  if (l3_xbar.isDefined) {
111    val errorDevice = LazyModule(new TLError(
112      params = DevNullParams(
113        address = Seq(AddressSet(0x0, 0x7fffffffL)),
114        maxAtomic = 8,
115        maxTransfer = 64),
116      beatBytes = L3InnerBusWidth / 8
117    ))
118    errorDevice.node :=
119      l3_xbar.get :=
120      TLFIFOFixer() :=
121      TLWidthWidget(32) :=
122      AXI4ToTL() :=
123      AXI4UserYanker(Some(1)) :=
124      AXI4Fragmenter() :=
125      AXI4Buffer() :=
126      AXI4Buffer() :=
127      AXI4IdIndexer(1) :=
128      l3FrontendAXI4Node
129  }
130
131  val dma = InModuleBody {
132    l3FrontendAXI4Node.makeIOs()
133  }
134}
135
136trait HaveAXI4MemPort {
137  this: BaseSoC =>
138  val device = new MemoryDevice
139  // 36-bit physical address
140  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
141  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
142    AXI4SlavePortParameters(
143      slaves = Seq(
144        AXI4SlaveParameters(
145          address = memRange,
146          regionType = RegionType.UNCACHED,
147          executable = true,
148          supportsRead = TransferSizes(1, L3BlockSize),
149          supportsWrite = TransferSizes(1, L3BlockSize),
150          interleavedId = Some(0),
151          resources = device.reg("mem")
152        )
153      ),
154      beatBytes = L3OuterBusWidth / 8,
155      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
156    )
157  ))
158
159  val mem_xbar = TLXbar()
160  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
161  val axi4mem_node = AXI4IdentityNode()
162
163  if (enableCHI) {
164    axi4mem_node :=
165      soc_xbar.get
166  } else {
167    mem_xbar :=*
168      TLBuffer.chainNode(2) :=
169      TLCacheCork() :=
170      l3_mem_pmu :=
171      TLClientsMerger() :=
172      TLXbar() :=*
173      bankedNode.get
174
175    mem_xbar :=
176      TLWidthWidget(8) :=
177      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
178      peripheralXbar.get
179
180    axi4mem_node :=
181      TLToAXI4() :=
182      TLSourceShrinker(64) :=
183      TLWidthWidget(L3OuterBusWidth / 8) :=
184      TLBuffer.chainNode(2) :=
185      mem_xbar
186  }
187
188  memAXI4SlaveNode :=
189    AXI4Buffer() :=
190    AXI4Buffer() :=
191    AXI4Buffer() :=
192    AXI4IdIndexer(idBits = 14) :=
193    AXI4UserYanker() :=
194    AXI4Deinterleaver(L3BlockSize) :=
195    axi4mem_node
196
197  val memory = InModuleBody {
198    memAXI4SlaveNode.makeIOs()
199  }
200}
201
202trait HaveAXI4PeripheralPort { this: BaseSoC =>
203  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
204  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
205  val uartRange = AddressSet(0x40600000, 0x3f)
206  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
207  val uartParams = AXI4SlaveParameters(
208    address = Seq(uartRange),
209    regionType = RegionType.UNCACHED,
210    supportsRead = TransferSizes(1, 32),
211    supportsWrite = TransferSizes(1, 32),
212    resources = uartDevice.reg
213  )
214  val peripheralRange = AddressSet(
215    0x0, 0x7fffffff
216  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
217  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
218    Seq(AXI4SlaveParameters(
219      address = peripheralRange,
220      regionType = RegionType.UNCACHED,
221      supportsRead = TransferSizes(1, 32),
222      supportsWrite = TransferSizes(1, 32),
223      interleavedId = Some(0)
224    ), uartParams),
225    beatBytes = 8
226  )))
227
228  val axi4peripheral_node = AXI4IdentityNode()
229  val error_xbar = Option.when(enableCHI)(TLXbar())
230
231  peripheralNode :=
232    AXI4UserYanker() :=
233    AXI4IdIndexer(idBits = 2) :=
234    AXI4Buffer() :=
235    AXI4Buffer() :=
236    AXI4Buffer() :=
237    AXI4Buffer() :=
238    AXI4UserYanker() :=
239    // AXI4Deinterleaver(8) :=
240    axi4peripheral_node
241
242  if (enableCHI) {
243    val error = LazyModule(new TLError(
244      params = DevNullParams(
245        address = Seq(AddressSet(0x1000000000L, 0xfffffffffL)),
246        maxAtomic = 8,
247        maxTransfer = 64),
248      beatBytes = 8
249    ))
250    error.node := error_xbar.get
251    axi4peripheral_node :=
252      AXI4Deinterleaver(8) :=
253      TLToAXI4() :=
254      error_xbar.get :=
255      TLFIFOFixer() :=
256      TLWidthWidget(L3OuterBusWidth / 8) :=
257      AXI4ToTL() :=
258      AXI4UserYanker() :=
259      soc_xbar.get
260  } else {
261    axi4peripheral_node :=
262      AXI4Deinterleaver(8) :=
263      TLToAXI4() :=
264      TLBuffer.chainNode(3) :=
265      peripheralXbar.get
266  }
267
268  val peripheral = InModuleBody {
269    peripheralNode.makeIOs()
270  }
271
272}
273
274class MemMisc()(implicit p: Parameters) extends BaseSoC
275  with HaveAXI4MemPort
276  with PMAConst
277  with HaveAXI4PeripheralPort
278{
279
280  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
281  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
282
283  val l3_in = TLTempNode()
284  val l3_out = TLTempNode()
285
286  val device_xbar = Option.when(enableCHI)(TLXbar())
287  device_xbar.foreach(_ := error_xbar.get)
288
289  if (l3_banked_xbar.isDefined) {
290    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
291    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
292  }
293  bankedNode match {
294    case Some(bankBinder) =>
295      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
296    case None =>
297  }
298
299  if(soc.L3CacheParamsOpt.isEmpty){
300    l3_out :*= l3_in
301  }
302
303  if (!enableCHI) {
304    for (port <- peripheral_ports.get) {
305      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
306    }
307  }
308
309  core_to_l3_ports.foreach { case _ =>
310    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
311      l3_banked_xbar.get :=*
312        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
313        TLBuffer() :=
314        core_out
315    }
316  }
317
318  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
319  if (enableCHI) { clint.node := device_xbar.get }
320  else { clint.node := peripheralXbar.get }
321
322  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
323    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
324    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
325      val in = IO(Input(Vec(num, Bool())))
326      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
327    }
328    lazy val module = new IntSourceNodeToModuleImp(this)
329  }
330
331  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
332  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
333
334  plic.intnode := plicSource.sourceNode
335  if (enableCHI) { plic.node := device_xbar.get }
336  else { plic.node := peripheralXbar.get }
337
338  val pll_node = TLRegisterNode(
339    address = Seq(AddressSet(0x3a000000L, 0xfff)),
340    device = new SimpleDevice("pll_ctrl", Seq()),
341    beatBytes = 8,
342    concurrency = 1
343  )
344  if (enableCHI) { pll_node := device_xbar.get }
345  else { pll_node := peripheralXbar.get }
346
347  val debugModule = LazyModule(new DebugModule(NumCores)(p))
348  if (enableCHI) {
349    debugModule.debug.node := device_xbar.get
350    // TODO: l3_xbar
351    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
352      error_xbar.get := sb2tl.node
353    }
354  } else {
355    debugModule.debug.node := peripheralXbar.get
356    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
357      l3_xbar.get := TLBuffer() := sb2tl.node
358    }
359  }
360
361  val pma = LazyModule(new TLPMA)
362  if (enableCHI) {
363    pma.node := TLBuffer.chainNode(4) := device_xbar.get
364  } else {
365    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
366  }
367
368  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
369
370    val debug_module_io = IO(new debugModule.DebugModuleIO)
371    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
372    val rtc_clock = IO(Input(Bool()))
373    val pll0_lock = IO(Input(Bool()))
374    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
375    val cacheable_check = IO(new TLPMAIO)
376
377    debugModule.module.io <> debug_module_io
378
379    // sync external interrupts
380    require(plicSource.module.in.length == ext_intrs.getWidth)
381    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
382      val ext_intr_sync = RegInit(0.U(3.W))
383      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
384      plic_in := ext_intr_sync(2)
385    }
386
387    pma.module.io <> cacheable_check
388
389    // positive edge sampling of the lower-speed rtc_clock
390    val rtcTick = RegInit(0.U(3.W))
391    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
392    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
393
394    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
395    val pll_lock = RegNext(next = pll0_lock, init = false.B)
396
397    pll0_ctrl <> VecInit(pll_ctrl_regs)
398
399    pll_node.regmap(
400      0x000 -> RegFieldGroup(
401        "Pll", Some("PLL ctrl regs"),
402        pll_ctrl_regs.zipWithIndex.map{
403          case (r, i) => RegField(32, r, RegFieldDesc(
404            s"PLL_ctrl_$i",
405            desc = s"PLL ctrl register #$i"
406          ))
407        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
408          "PLL_lock",
409          "PLL lock register"
410        ))
411      )
412    )
413  }
414
415  lazy val module = new SoCMiscImp(this)
416}
417
418class SoCMisc()(implicit p: Parameters) extends MemMisc
419  with HaveSlaveAXI4Port
420
421