xref: /XiangShan/src/main/scala/system/SoC.scala (revision ae44e2b70b48774aac714529385f8df2bd7ed4ec) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import huancun._
30import top.BusPerfMonitor
31import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
32import xiangshan.backend.fu.PMAConst
33import xiangshan.{DebugOptionsKey, XSTileKey}
34import coupledL2.EnableCHI
35
36case object SoCParamsKey extends Field[SoCParameters]
37
38case class SoCParameters
39(
40  EnableILA: Boolean = false,
41  PAddrBits: Int = 36,
42  extIntrs: Int = 64,
43  L3NBanks: Int = 4,
44  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
45    name = "L3",
46    level = 3,
47    ways = 8,
48    sets = 2048 // 1MB per bank
49  )),
50  XSTopPrefix: Option[String] = None,
51  NodeIDWidth: Int = 7
52){
53  // L3 configurations
54  val L3InnerBusWidth = 256
55  val L3BlockSize = 64
56  // on chip network configurations
57  val L3OuterBusWidth = 256
58}
59
60trait HasSoCParameter {
61  implicit val p: Parameters
62
63  val soc = p(SoCParamsKey)
64  val debugOpts = p(DebugOptionsKey)
65  val tiles = p(XSTileKey)
66  val enableCHI = p(EnableCHI)
67
68  val NumCores = tiles.size
69  val EnableILA = soc.EnableILA
70
71  // L3 configurations
72  val L3InnerBusWidth = soc.L3InnerBusWidth
73  val L3BlockSize = soc.L3BlockSize
74  val L3NBanks = soc.L3NBanks
75
76  // on chip network configurations
77  val L3OuterBusWidth = soc.L3OuterBusWidth
78
79  val NrExtIntr = soc.extIntrs
80}
81
82class ILABundle extends Bundle {}
83
84
85abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
86  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
87  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
88  val l3_xbar = Option.when(!enableCHI)(TLXbar())
89  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
90
91  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
92}
93
94// We adapt the following three traits from rocket-chip.
95// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
96trait HaveSlaveAXI4Port {
97  this: BaseSoC =>
98
99  val idBits = 14
100
101  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
102    Seq(AXI4MasterParameters(
103      name = "dma",
104      id = IdRange(0, 1 << idBits)
105    ))
106  )))
107
108  if (l3_xbar.isDefined) {
109    val errorDevice = LazyModule(new TLError(
110      params = DevNullParams(
111        address = Seq(AddressSet(0x0, 0x7fffffffL)),
112        maxAtomic = 8,
113        maxTransfer = 64),
114      beatBytes = L3InnerBusWidth / 8
115    ))
116    errorDevice.node :=
117      l3_xbar.get :=
118      TLFIFOFixer() :=
119      TLWidthWidget(32) :=
120      AXI4ToTL() :=
121      AXI4UserYanker(Some(1)) :=
122      AXI4Fragmenter() :=
123      AXI4Buffer() :=
124      AXI4Buffer() :=
125      AXI4IdIndexer(1) :=
126      l3FrontendAXI4Node
127  }
128
129  val dma = InModuleBody {
130    l3FrontendAXI4Node.makeIOs()
131  }
132}
133
134trait HaveAXI4MemPort {
135  this: BaseSoC =>
136  val device = new MemoryDevice
137  // 36-bit physical address
138  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
139  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
140    AXI4SlavePortParameters(
141      slaves = Seq(
142        AXI4SlaveParameters(
143          address = memRange,
144          regionType = RegionType.UNCACHED,
145          executable = true,
146          supportsRead = TransferSizes(1, L3BlockSize),
147          supportsWrite = TransferSizes(1, L3BlockSize),
148          interleavedId = Some(0),
149          resources = device.reg("mem")
150        )
151      ),
152      beatBytes = L3OuterBusWidth / 8,
153      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
154    )
155  ))
156
157  val mem_xbar = TLXbar()
158  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
159  val axi4mem_node = AXI4IdentityNode()
160
161  if (enableCHI) {
162    axi4mem_node :=
163      soc_xbar.get
164  } else {
165    mem_xbar :=*
166      TLBuffer.chainNode(2) :=
167      TLCacheCork() :=
168      l3_mem_pmu :=
169      TLClientsMerger() :=
170      TLXbar() :=*
171      bankedNode.get
172
173    mem_xbar :=
174      TLWidthWidget(8) :=
175      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
176      peripheralXbar.get
177
178    axi4mem_node :=
179      TLToAXI4() :=
180      TLSourceShrinker(64) :=
181      TLWidthWidget(L3OuterBusWidth / 8) :=
182      TLBuffer.chainNode(2) :=
183      mem_xbar
184  }
185
186  memAXI4SlaveNode :=
187    AXI4Buffer() :=
188    AXI4Buffer() :=
189    AXI4Buffer() :=
190    AXI4IdIndexer(idBits = 14) :=
191    AXI4UserYanker() :=
192    AXI4Deinterleaver(L3BlockSize) :=
193    axi4mem_node
194
195  val memory = InModuleBody {
196    memAXI4SlaveNode.makeIOs()
197  }
198}
199
200trait HaveAXI4PeripheralPort { this: BaseSoC =>
201  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
202  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
203  val uartRange = AddressSet(0x40600000, 0x3f)
204  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
205  val uartParams = AXI4SlaveParameters(
206    address = Seq(uartRange),
207    regionType = RegionType.UNCACHED,
208    supportsRead = TransferSizes(1, 32),
209    supportsWrite = TransferSizes(1, 32),
210    resources = uartDevice.reg
211  )
212  val peripheralRange = AddressSet(
213    0x0, 0x7fffffff
214  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
215  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
216    Seq(AXI4SlaveParameters(
217      address = peripheralRange,
218      regionType = RegionType.UNCACHED,
219      supportsRead = TransferSizes(1, 32),
220      supportsWrite = TransferSizes(1, 32),
221      interleavedId = Some(0)
222    ), uartParams),
223    beatBytes = 8
224  )))
225
226  val axi4peripheral_node = AXI4IdentityNode()
227  val error_xbar = Option.when(enableCHI)(TLXbar())
228
229  peripheralNode :=
230    AXI4UserYanker() :=
231    AXI4IdIndexer(idBits = 2) :=
232    AXI4Buffer() :=
233    AXI4Buffer() :=
234    AXI4Buffer() :=
235    AXI4Buffer() :=
236    AXI4UserYanker() :=
237    // AXI4Deinterleaver(8) :=
238    axi4peripheral_node
239
240  if (enableCHI) {
241    val error = LazyModule(new TLError(
242      params = DevNullParams(
243        address = Seq(AddressSet(0x1000000000L, 0xfffffffffL)),
244        maxAtomic = 8,
245        maxTransfer = 64),
246      beatBytes = 8
247    ))
248    error.node := error_xbar.get
249    axi4peripheral_node :=
250      AXI4Deinterleaver(8) :=
251      TLToAXI4() :=
252      error_xbar.get :=
253      TLFIFOFixer() :=
254      TLWidthWidget(L3OuterBusWidth / 8) :=
255      AXI4ToTL() :=
256      AXI4UserYanker() :=
257      soc_xbar.get
258  } else {
259    axi4peripheral_node :=
260      AXI4Deinterleaver(8) :=
261      TLToAXI4() :=
262      TLBuffer.chainNode(3) :=
263      peripheralXbar.get
264  }
265
266  val peripheral = InModuleBody {
267    peripheralNode.makeIOs()
268  }
269
270}
271
272class MemMisc()(implicit p: Parameters) extends BaseSoC
273  with HaveAXI4MemPort
274  with PMAConst
275  with HaveAXI4PeripheralPort
276{
277
278  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
279  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
280
281  val l3_in = TLTempNode()
282  val l3_out = TLTempNode()
283
284  val device_xbar = Option.when(enableCHI)(TLXbar())
285  device_xbar.foreach(_ := error_xbar.get)
286
287  if (l3_banked_xbar.isDefined) {
288    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
289    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
290  }
291  bankedNode match {
292    case Some(bankBinder) =>
293      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
294    case None =>
295  }
296
297  if(soc.L3CacheParamsOpt.isEmpty){
298    l3_out :*= l3_in
299  }
300
301  if (!enableCHI) {
302    for (port <- peripheral_ports.get) {
303      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
304    }
305  }
306
307  core_to_l3_ports.foreach { case _ =>
308    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
309      l3_banked_xbar.get :=*
310        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
311        TLBuffer() :=
312        core_out
313    }
314  }
315
316  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
317  if (enableCHI) { clint.node := device_xbar.get }
318  else { clint.node := peripheralXbar.get }
319
320  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
321    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
322    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
323      val in = IO(Input(Vec(num, Bool())))
324      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
325    }
326    lazy val module = new IntSourceNodeToModuleImp(this)
327  }
328
329  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
330  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
331
332  plic.intnode := plicSource.sourceNode
333  if (enableCHI) { plic.node := device_xbar.get }
334  else { plic.node := peripheralXbar.get }
335
336  val pll_node = TLRegisterNode(
337    address = Seq(AddressSet(0x3a000000L, 0xfff)),
338    device = new SimpleDevice("pll_ctrl", Seq()),
339    beatBytes = 8,
340    concurrency = 1
341  )
342  if (enableCHI) { pll_node := device_xbar.get }
343  else { pll_node := peripheralXbar.get }
344
345  val debugModule = LazyModule(new DebugModule(NumCores)(p))
346  if (enableCHI) {
347    debugModule.debug.node := device_xbar.get
348    // TODO: l3_xbar
349    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
350      error_xbar.get := sb2tl.node
351    }
352  } else {
353    debugModule.debug.node := peripheralXbar.get
354    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
355      l3_xbar.get := TLBuffer() := sb2tl.node
356    }
357  }
358
359  val pma = LazyModule(new TLPMA)
360  if (enableCHI) {
361    pma.node := TLBuffer.chainNode(4) := device_xbar.get
362  } else {
363    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
364  }
365
366  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
367
368    val debug_module_io = IO(new debugModule.DebugModuleIO)
369    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
370    val rtc_clock = IO(Input(Bool()))
371    val pll0_lock = IO(Input(Bool()))
372    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
373    val cacheable_check = IO(new TLPMAIO)
374
375    debugModule.module.io <> debug_module_io
376
377    // sync external interrupts
378    require(plicSource.module.in.length == ext_intrs.getWidth)
379    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
380      val ext_intr_sync = RegInit(0.U(3.W))
381      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
382      plic_in := ext_intr_sync(2)
383    }
384
385    pma.module.io <> cacheable_check
386
387    // positive edge sampling of the lower-speed rtc_clock
388    val rtcTick = RegInit(0.U(3.W))
389    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
390    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
391
392    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
393    val pll_lock = RegNext(next = pll0_lock, init = false.B)
394
395    pll0_ctrl <> VecInit(pll_ctrl_regs)
396
397    pll_node.regmap(
398      0x000 -> RegFieldGroup(
399        "Pll", Some("PLL ctrl regs"),
400        pll_ctrl_regs.zipWithIndex.map{
401          case (r, i) => RegField(32, r, RegFieldDesc(
402            s"PLL_ctrl_$i",
403            desc = s"PLL ctrl register #$i"
404          ))
405        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
406          "PLL_lock",
407          "PLL lock register"
408        ))
409      )
410    )
411  }
412
413  lazy val module = new SoCMiscImp(this)
414}
415
416class SoCMisc()(implicit p: Parameters) extends MemMisc
417  with HaveSlaveAXI4Port
418
419