xref: /XiangShan/src/main/scala/system/SoC.scala (revision a273862e37f1d43bee748f2a6353320a2f52f6f4) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.DebugModule
23import freechips.rocketchip.amba.axi4.{AXI4Buffer, AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters, AXI4ToTL, AXI4UserYanker}
24import freechips.rocketchip.devices.tilelink.{CLINT, CLINTParams, DevNullParams, PLICParams, TLError, TLPLIC}
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
28import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
29import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLCacheCork, TLFIFOFixer, TLTempNode, TLToAXI4, TLWidthWidget, TLXbar}
30import huancun.debug.TLLogger
31import huancun.{CacheParameters, HCCacheParameters, BankedXbar}
32import top.BusPerfMonitor
33
34case object SoCParamsKey extends Field[SoCParameters]
35
36case class SoCParameters
37(
38  cores: List[XSCoreParameters],
39  EnableILA: Boolean = false,
40  extIntrs: Int = 150,
41  L3NBanks: Int = 4,
42  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
43    name = "l3",
44    level = 3,
45    ways = 8,
46    sets = 2048 // 1MB per bank
47  ))
48){
49  val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
50  // L3 configurations
51  val L3InnerBusWidth = 256
52  val L3BlockSize = 64
53  // on chip network configurations
54  val L3OuterBusWidth = 256
55}
56
57trait HasSoCParameter {
58  implicit val p: Parameters
59
60  val soc = p(SoCParamsKey)
61  val debugOpts = p(DebugOptionsKey)
62  val NumCores = soc.cores.size
63  val EnableILA = soc.EnableILA
64
65  // L3 configurations
66  val L3InnerBusWidth = soc.L3InnerBusWidth
67  val L3BlockSize = soc.L3BlockSize
68  val L3NBanks = soc.L3NBanks
69
70  // on chip network configurations
71  val L3OuterBusWidth = soc.L3OuterBusWidth
72
73  val NrExtIntr = soc.extIntrs
74}
75
76class ILABundle extends Bundle {}
77
78
79abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
80  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
81  val peripheralXbar = TLXbar()
82  val l3_xbar = TLXbar()
83  val l3_banked_xbar = BankedXbar(soc.cores.head.L2NBanks)
84}
85
86// We adapt the following three traits from rocket-chip.
87// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
88trait HaveSlaveAXI4Port {
89  this: BaseSoC =>
90
91  val idBits = 14
92
93  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
94    Seq(AXI4MasterParameters(
95      name = "dma",
96      id = IdRange(0, 1 << idBits)
97    ))
98  )))
99  private val errorDevice = LazyModule(new TLError(
100    params = DevNullParams(
101      address = Seq(AddressSet(0x0, 0x7fffffffL)),
102      maxAtomic = 8,
103      maxTransfer = 64),
104    beatBytes = L3InnerBusWidth / 8
105  ))
106  private val error_xbar = TLXbar()
107
108  error_xbar :=
109    TLFIFOFixer() :=
110    TLWidthWidget(16) :=
111    AXI4ToTL() :=
112    AXI4UserYanker(Some(1)) :=
113    AXI4Fragmenter() :=
114    AXI4IdIndexer(1) :=
115    l3FrontendAXI4Node
116  errorDevice.node := error_xbar
117  l3_xbar :=
118    TLBuffer() :=
119    error_xbar
120
121  val dma = InModuleBody {
122    l3FrontendAXI4Node.makeIOs()
123  }
124}
125
126trait HaveAXI4MemPort {
127  this: BaseSoC =>
128  val device = new MemoryDevice
129  // 40-bit physical address
130  val memRange = AddressSet(0x00000000L, 0xffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
131  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
132    AXI4SlavePortParameters(
133      slaves = Seq(
134        AXI4SlaveParameters(
135          address = memRange,
136          regionType = RegionType.UNCACHED,
137          executable = true,
138          supportsRead = TransferSizes(1, L3BlockSize),
139          supportsWrite = TransferSizes(1, L3BlockSize),
140          interleavedId = Some(0),
141          resources = device.reg("mem")
142        )
143      ),
144      beatBytes = L3OuterBusWidth / 8
145    )
146  ))
147
148  def mem_buffN(n: Int) = {
149    val buffers = (0 until n).map(_ => AXI4Buffer())
150    buffers.reduce((l, r) => l := r)
151    (buffers.head, buffers.last)
152  }
153  val mem_xbar = TLXbar()
154  mem_xbar :=* TLCacheCork() :=* bankedNode
155  val (buf_l, buf_r) = mem_buffN(5)
156  memAXI4SlaveNode := buf_l
157  buf_r :=
158    AXI4UserYanker() :=
159    AXI4Deinterleaver(L3BlockSize) :=
160    TLToAXI4() :=
161    TLWidthWidget(L3OuterBusWidth / 8) :=
162    mem_xbar
163
164  val memory = InModuleBody {
165    memAXI4SlaveNode.makeIOs()
166  }
167}
168
169trait HaveAXI4PeripheralPort { this: BaseSoC =>
170  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
171  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
172  val uartRange = AddressSet(0x40600000, 0xf)
173  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
174  val uartParams = AXI4SlaveParameters(
175    address = Seq(uartRange),
176    regionType = RegionType.UNCACHED,
177    supportsRead = TransferSizes(1, 8),
178    supportsWrite = TransferSizes(1, 8),
179    resources = uartDevice.reg
180  )
181  val peripheralRange = AddressSet(
182    0x0, 0x7fffffff
183  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
184  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
185    Seq(AXI4SlaveParameters(
186      address = peripheralRange,
187      regionType = RegionType.UNCACHED,
188      supportsRead = TransferSizes(1, 8),
189      supportsWrite = TransferSizes(1, 8),
190      interleavedId = Some(0)
191    ), uartParams),
192    beatBytes = 8
193  )))
194
195  peripheralNode :=
196    AXI4UserYanker() :=
197    AXI4Deinterleaver(8) :=
198    TLToAXI4() :=
199    peripheralXbar
200
201  val peripheral = InModuleBody {
202    peripheralNode.makeIOs()
203  }
204
205}
206
207class SoCMisc()(implicit p: Parameters) extends BaseSoC
208  with HaveAXI4MemPort
209  with HaveAXI4PeripheralPort
210  with HaveSlaveAXI4Port
211{
212  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
213  val core_to_l3_ports = Array.fill(NumCores) { TLTempNode() }
214
215  val l3_in = TLTempNode()
216  val l3_out = TLTempNode()
217  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
218
219  l3_in :*= l3_banked_xbar
220  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3_out
221
222  if(soc.L3CacheParamsOpt.isEmpty){
223    l3_out :*= l3_in
224  }
225
226  for(port <- peripheral_ports) {
227    peripheralXbar := port
228  }
229
230  for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
231    l3_banked_xbar :=* TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=* core_out
232  }
233  l3_banked_xbar :=* BankBinder(soc.cores.head.L2NBanks, L3BlockSize) :*= l3_xbar
234
235  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
236  clint.node := peripheralXbar
237
238  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
239    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
240    lazy val module = new LazyModuleImp(this){
241      val in = IO(Input(Vec(num, Bool())))
242      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
243    }
244  }
245
246  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
247  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
248
249  plic.intnode := plicSource.sourceNode
250  plic.node := peripheralXbar
251
252  val debugModule = LazyModule(new DebugModule(NumCores)(p))
253  debugModule.debug.node := peripheralXbar
254  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
255    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
256  }
257
258  lazy val module = new LazyModuleImp(this){
259
260    val debug_module_io = IO(chiselTypeOf(debugModule.module.io))
261    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
262
263    debugModule.module.io <> debug_module_io
264    plicSource.module.in := ext_intrs.asBools
265
266    val freq = 100
267    val cnt = RegInit(freq.U)
268    val tick = cnt === 0.U
269    cnt := Mux(tick, freq.U, cnt - 1.U)
270    clint.module.io.rtcTick := tick
271  }
272}
273