1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package system 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt} 23import freechips.rocketchip.amba.axi4._ 24import freechips.rocketchip.devices.debug.DebugModuleKey 25import freechips.rocketchip.devices.tilelink._ 26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes} 27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple} 28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup} 29import freechips.rocketchip.tilelink._ 30import freechips.rocketchip.util.AsyncQueueParams 31import huancun._ 32import top.BusPerfMonitor 33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst} 35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey} 36import coupledL2.{EnableCHI, L2Param} 37import coupledL2.tl2chi.CHIIssue 38import openLLC.OpenLLCParam 39 40case object SoCParamsKey extends Field[SoCParameters] 41case object CVMParamskey extends Field[CVMParameters] 42 43case class CVMParameters 44( 45 MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff), 46 KeyIDBits: Int = 0, 47 MemencPipes: Int = 4, 48 HasMEMencryption: Boolean = false, 49 HasDelayNoencryption: Boolean = false, // Test specific 50) 51 52case class SoCParameters 53( 54 EnableILA: Boolean = false, 55 PAddrBits: Int = 48, 56 PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)), 57 PMAConfigs: Seq[PMAConfigEntry] = Seq( 58 PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3), 59 PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true), 60 PMAConfigEntry(0x80000000L, a = 1, w = true, r = true), 61 PMAConfigEntry(0x3A000000L, a = 1), 62 PMAConfigEntry(0x39002000L, a = 1, w = true, r = true), 63 PMAConfigEntry(0x39000000L, a = 1, w = true, r = true), 64 PMAConfigEntry(0x38022000L, a = 1, w = true, r = true), 65 PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true), 66 PMAConfigEntry(0x38020000L, a = 1, w = true, r = true), 67 PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable? 68 PMAConfigEntry(0x30010000L, a = 1, w = true, r = true), 69 PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true), 70 PMAConfigEntry(0x10000000L, a = 1, w = true, r = true), 71 PMAConfigEntry(0) 72 ), 73 CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1), 74 BEURange: AddressSet = AddressSet(0x38010000L, 0xfff), 75 PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1), 76 PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff), 77 UARTLiteForDTS: Boolean = true, // should be false in SimMMIO 78 extIntrs: Int = 64, 79 L3NBanks: Int = 4, 80 L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 81 name = "L3", 82 level = 3, 83 ways = 8, 84 sets = 2048 // 1MB per bank 85 )), 86 OpenLLCParamsOpt: Option[OpenLLCParam] = None, 87 XSTopPrefix: Option[String] = None, 88 NodeIDWidthList: Map[String, Int] = Map( 89 "B" -> 7, 90 "C" -> 9, 91 "E.b" -> 11 92 ), 93 NumHart: Int = 64, 94 NumIRFiles: Int = 7, 95 NumIRSrc: Int = 256, 96 UseXSNoCTop: Boolean = false, 97 UseXSNoCDiffTop: Boolean = false, 98 IMSICUseTL: Boolean = false, 99 EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)), 100 EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)) 101){ 102 require( 103 L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty, 104 "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined" 105 ) 106 // L3 configurations 107 val L3InnerBusWidth = 256 108 val L3BlockSize = 64 109 // on chip network configurations 110 val L3OuterBusWidth = 256 111 val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf) 112} 113 114trait HasSoCParameter { 115 implicit val p: Parameters 116 117 val soc = p(SoCParamsKey) 118 val cvm = p(CVMParamskey) 119 val debugOpts = p(DebugOptionsKey) 120 val tiles = p(XSTileKey) 121 val enableCHI = p(EnableCHI) 122 val issue = p(CHIIssue) 123 124 val NumCores = tiles.size 125 val EnableILA = soc.EnableILA 126 127 // Parameters for trace extension 128 val TraceTraceGroupNum = tiles.head.traceParams.TraceGroupNum 129 val TraceCauseWidth = tiles.head.XLEN 130 val TraceTvalWidth = tiles.head.traceParams.IaddrWidth 131 val TracePrivWidth = tiles.head.traceParams.PrivWidth 132 val TraceIaddrWidth = tiles.head.traceParams.IaddrWidth 133 val TraceItypeWidth = tiles.head.traceParams.ItypeWidth 134 val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2) 135 val TraceIlastsizeWidth = tiles.head.traceParams.IlastsizeWidth 136 137 // L3 configurations 138 val L3InnerBusWidth = soc.L3InnerBusWidth 139 val L3BlockSize = soc.L3BlockSize 140 val L3NBanks = soc.L3NBanks 141 142 // on chip network configurations 143 val L3OuterBusWidth = soc.L3OuterBusWidth 144 145 val NrExtIntr = soc.extIntrs 146 147 val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles 148 149 val NumIRSrc = soc.NumIRSrc 150 151 val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined) 152 soc.EnableCHIAsyncBridge else None 153 val EnableClintAsyncBridge = soc.EnableClintAsyncBridge 154 155 def HasMEMencryption = cvm.HasMEMencryption 156 require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)) , 157 "HasMEMencryption most set with KeyIDBits > 0") 158} 159 160trait HasPeripheralRanges { 161 implicit val p: Parameters 162 163 private def cvm = p(CVMParamskey) 164 private def soc = p(SoCParamsKey) 165 private def dm = p(DebugModuleKey) 166 private def pmParams = p(PMParameKey) 167 168 private def mmpma = pmParams.mmpma 169 170 def onChipPeripheralRanges: Map[String, AddressSet] = Map( 171 "CLINT" -> soc.CLINTRange, 172 "BEU" -> soc.BEURange, 173 "PLIC" -> soc.PLICRange, 174 "PLL" -> soc.PLLRange, 175 "UART" -> soc.UARTLiteRange, 176 "DEBUG" -> dm.get.address, 177 "MMPMA" -> AddressSet(mmpma.address, mmpma.mask) 178 ) ++ ( 179 if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false)) 180 Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff)) 181 else 182 Map() 183 ) ++ ( 184 if (cvm.HasMEMencryption) 185 Map("MEMENC" -> cvm.MEMENCRange) 186 else 187 Map() 188 ) 189 190 def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) => 191 acc.flatMap(_.subtract(x)) 192 } 193} 194 195class ILABundle extends Bundle {} 196 197 198abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges { 199 val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize)) 200 val peripheralXbar = Option.when(!enableCHI)(TLXbar()) 201 val l3_xbar = Option.when(!enableCHI)(TLXbar()) 202 val l3_banked_xbar = Option.when(!enableCHI)(TLXbar()) 203 204 val soc_xbar = Option.when(enableCHI)(AXI4Xbar()) 205} 206 207// We adapt the following three traits from rocket-chip. 208// Source: rocket-chip/src/main/scala/subsystem/Ports.scala 209trait HaveSlaveAXI4Port { 210 this: BaseSoC => 211 212 val idBits = 14 213 214 val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters( 215 Seq(AXI4MasterParameters( 216 name = "dma", 217 id = IdRange(0, 1 << idBits) 218 )) 219 ))) 220 221 if (l3_xbar.isDefined) { 222 val errorDevice = LazyModule(new TLError( 223 params = DevNullParams( 224 address = Seq(AddressSet(0x0, 0x7fffffffL)), 225 maxAtomic = 8, 226 maxTransfer = 64), 227 beatBytes = L3InnerBusWidth / 8 228 )) 229 errorDevice.node := 230 l3_xbar.get := 231 TLFIFOFixer() := 232 TLWidthWidget(32) := 233 AXI4ToTL() := 234 AXI4UserYanker(Some(1)) := 235 AXI4Fragmenter() := 236 AXI4Buffer() := 237 AXI4Buffer() := 238 AXI4IdIndexer(1) := 239 l3FrontendAXI4Node 240 } 241 242 val dma = InModuleBody { 243 l3FrontendAXI4Node.makeIOs() 244 } 245} 246 247trait HaveAXI4MemPort { 248 this: BaseSoC => 249 val device = new MemoryDevice 250 // 48-bit physical address 251 val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL)) 252 val memAXI4SlaveNode = AXI4SlaveNode(Seq( 253 AXI4SlavePortParameters( 254 slaves = Seq( 255 AXI4SlaveParameters( 256 address = memRange, 257 regionType = RegionType.UNCACHED, 258 executable = true, 259 supportsRead = TransferSizes(1, L3BlockSize), 260 supportsWrite = TransferSizes(1, L3BlockSize), 261 interleavedId = Some(0), 262 resources = device.reg("mem") 263 ) 264 ), 265 beatBytes = L3OuterBusWidth / 8, 266 requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey), 267 ) 268 )) 269 270 val mem_xbar = TLXbar() 271 val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true) 272 val axi4mem_node = AXI4IdentityNode() 273 274 if (enableCHI) { 275 axi4mem_node := 276 soc_xbar.get 277 } else { 278 mem_xbar :=* 279 TLBuffer.chainNode(2) := 280 TLCacheCork() := 281 l3_mem_pmu := 282 TLClientsMerger() := 283 TLXbar() :=* 284 bankedNode.get 285 286 mem_xbar := 287 TLWidthWidget(8) := 288 TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) := 289 peripheralXbar.get 290 291 axi4mem_node := 292 TLToAXI4() := 293 TLSourceShrinker(64) := 294 TLWidthWidget(L3OuterBusWidth / 8) := 295 TLBuffer.chainNode(2) := 296 mem_xbar 297 } 298 val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange))) 299 if (HasMEMencryption) { 300 memAXI4SlaveNode := 301 AXI4Buffer() := 302 AXI4Buffer() := 303 AXI4Buffer() := 304 AXI4IdIndexer(idBits = 14) := 305 AXI4UserYanker() := 306 axi4memencrpty.get.node 307 308 axi4memencrpty.get.node := 309 AXI4Deinterleaver(L3BlockSize) := 310 axi4mem_node 311 } else { 312 memAXI4SlaveNode := 313 AXI4Buffer() := 314 AXI4Buffer() := 315 AXI4Buffer() := 316 AXI4IdIndexer(idBits = 14) := 317 AXI4UserYanker() := 318 AXI4Deinterleaver(L3BlockSize) := 319 axi4mem_node 320 } 321 322 323 val memory = InModuleBody { 324 memAXI4SlaveNode.makeIOs() 325 } 326} 327 328trait HaveAXI4PeripheralPort { this: BaseSoC => 329 val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite")) 330 val uartParams = AXI4SlaveParameters( 331 address = Seq(soc.UARTLiteRange), 332 regionType = RegionType.UNCACHED, 333 supportsRead = TransferSizes(1, 32), 334 supportsWrite = TransferSizes(1, 32), 335 resources = uartDevice.reg 336 ) 337 val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters( 338 Seq(AXI4SlaveParameters( 339 address = peripheralRange, 340 regionType = RegionType.UNCACHED, 341 supportsRead = TransferSizes(1, 32), 342 supportsWrite = TransferSizes(1, 32), 343 interleavedId = Some(0) 344 ), uartParams), 345 beatBytes = 8 346 ))) 347 348 val axi4peripheral_node = AXI4IdentityNode() 349 val error_xbar = Option.when(enableCHI)(TLXbar()) 350 351 peripheralNode := 352 AXI4UserYanker() := 353 AXI4IdIndexer(idBits = 2) := 354 AXI4Buffer() := 355 AXI4Buffer() := 356 AXI4Buffer() := 357 AXI4Buffer() := 358 AXI4UserYanker() := 359 // AXI4Deinterleaver(8) := 360 axi4peripheral_node 361 362 if (enableCHI) { 363 val error = LazyModule(new TLError( 364 params = DevNullParams( 365 address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)), 366 maxAtomic = 8, 367 maxTransfer = 64), 368 beatBytes = 8 369 )) 370 error.node := error_xbar.get 371 axi4peripheral_node := 372 AXI4Deinterleaver(8) := 373 TLToAXI4() := 374 error_xbar.get := 375 TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) := 376 TLFIFOFixer() := 377 TLWidthWidget(L3OuterBusWidth / 8) := 378 AXI4ToTL() := 379 AXI4UserYanker() := 380 soc_xbar.get 381 } else { 382 axi4peripheral_node := 383 AXI4Deinterleaver(8) := 384 TLToAXI4() := 385 TLBuffer.chainNode(3) := 386 peripheralXbar.get 387 } 388 389 val peripheral = InModuleBody { 390 peripheralNode.makeIOs() 391 } 392 393} 394 395class MemMisc()(implicit p: Parameters) extends BaseSoC 396 with HaveAXI4MemPort 397 with PMAConst 398 with HaveAXI4PeripheralPort 399{ 400 401 val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 402 val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() }) 403 404 val l3_in = TLTempNode() 405 val l3_out = TLTempNode() 406 407 val device_xbar = Option.when(enableCHI)(TLXbar()) 408 device_xbar.foreach(_ := error_xbar.get) 409 410 if (l3_banked_xbar.isDefined) { 411 l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get 412 l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get 413 } 414 bankedNode match { 415 case Some(bankBinder) => 416 bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out 417 case None => 418 } 419 420 if(soc.L3CacheParamsOpt.isEmpty){ 421 l3_out :*= l3_in 422 } 423 424 if (!enableCHI) { 425 for (port <- peripheral_ports.get) { 426 peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port 427 } 428 } 429 430 core_to_l3_ports.foreach { case _ => 431 for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){ 432 l3_banked_xbar.get :=* 433 TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=* 434 TLBuffer() := 435 core_out 436 } 437 } 438 439 val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8)) 440 if (enableCHI) { clint.node := device_xbar.get } 441 else { clint.node := peripheralXbar.get } 442 443 class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule { 444 val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1)) 445 class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 446 val in = IO(Input(Vec(num, Bool()))) 447 in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i } 448 } 449 lazy val module = new IntSourceNodeToModuleImp(this) 450 } 451 452 val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8)) 453 val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr)) 454 455 plic.intnode := plicSource.sourceNode 456 if (enableCHI) { plic.node := device_xbar.get } 457 else { plic.node := peripheralXbar.get } 458 459 val pll_node = TLRegisterNode( 460 address = Seq(soc.PLLRange), 461 device = new SimpleDevice("pll_ctrl", Seq()), 462 beatBytes = 8, 463 concurrency = 1 464 ) 465 if (enableCHI) { pll_node := device_xbar.get } 466 else { pll_node := peripheralXbar.get } 467 468 val debugModule = LazyModule(new DebugModule(NumCores)(p)) 469 if (enableCHI) { 470 debugModule.debug.node := device_xbar.get 471 // TODO: l3_xbar 472 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 473 error_xbar.get := sb2tl.node 474 } 475 } else { 476 debugModule.debug.node := peripheralXbar.get 477 debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => 478 l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node 479 } 480 } 481 482 val pma = LazyModule(new TLPMA) 483 if (enableCHI) { 484 pma.node := TLBuffer.chainNode(4) := device_xbar.get 485 if (HasMEMencryption) { 486 axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get 487 } 488 } else { 489 pma.node := TLBuffer.chainNode(4) := peripheralXbar.get 490 if (HasMEMencryption) { 491 axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get 492 } 493 } 494 495 class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 496 497 val debug_module_io = IO(new debugModule.DebugModuleIO) 498 val ext_intrs = IO(Input(UInt(NrExtIntr.W))) 499 val rtc_clock = IO(Input(Bool())) 500 val pll0_lock = IO(Input(Bool())) 501 val pll0_ctrl = IO(Output(Vec(6, UInt(32.W)))) 502 val cacheable_check = IO(new TLPMAIO) 503 val clintTime = IO(Output(ValidIO(UInt(64.W)))) 504 505 debugModule.module.io <> debug_module_io 506 507 // sync external interrupts 508 require(plicSource.module.in.length == ext_intrs.getWidth) 509 for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) { 510 val ext_intr_sync = RegInit(0.U(3.W)) 511 ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt) 512 plic_in := ext_intr_sync(2) 513 } 514 515 pma.module.io <> cacheable_check 516 517 if (HasMEMencryption) { 518 val cnt = Counter(true.B, 8)._1 519 axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool 520 axi4memencrpty.get.module.io.random_data := cnt(0).asBool 521 } 522 // positive edge sampling of the lower-speed rtc_clock 523 val rtcTick = RegInit(0.U(3.W)) 524 rtcTick := Cat(rtcTick(1, 0), rtc_clock) 525 clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2) 526 527 val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) } 528 val pll_lock = RegNext(next = pll0_lock, init = false.B) 529 530 clintTime := clint.module.io.time 531 532 pll0_ctrl <> VecInit(pll_ctrl_regs) 533 534 pll_node.regmap( 535 0x000 -> RegFieldGroup( 536 "Pll", Some("PLL ctrl regs"), 537 pll_ctrl_regs.zipWithIndex.map{ 538 case (r, i) => RegField(32, r, RegFieldDesc( 539 s"PLL_ctrl_$i", 540 desc = s"PLL ctrl register #$i" 541 )) 542 } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc( 543 "PLL_lock", 544 "PLL lock register" 545 )) 546 ) 547 ) 548 } 549 550 lazy val module = new SoCMiscImp(this) 551} 552 553class SoCMisc()(implicit p: Parameters) extends MemMisc 554 with HaveSlaveAXI4Port 555 556