xref: /XiangShan/src/main/scala/system/SoC.scala (revision 4b3d9f67355a9945cd5eca46929b89c130c43c26) 
1package system
2
3import chipsalliance.rocketchip.config.Parameters
4import device.{AXI4Timer, TLTimer}
5import chisel3._
6import chisel3.util._
7import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
8import freechips.rocketchip.tilelink.{TLBuffer, TLFuzzer, TLIdentityNode, TLXbar}
9import utils.DebugIdentityNode
10import xiangshan.{HasXSParameter, XSCore}
11import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
12import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet}
13import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4}
14import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams}
15import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver}
16
17case class SoCParameters
18(
19  NumCores: Integer = 1,
20  EnableILA: Boolean = false,
21  HasL2Cache: Boolean = false,
22  HasPrefetch: Boolean = false
23)
24
25trait HasSoCParameter extends HasXSParameter{
26  val soc = top.Parameters.get.socParameters
27  val NumCores = soc.NumCores
28  val EnableILA = soc.EnableILA
29  val HasL2cache = soc.HasL2Cache
30  val HasPrefetch = soc.HasPrefetch
31}
32
33class ILABundle extends Bundle {}
34
35
36class DummyCore()(implicit p: Parameters) extends LazyModule {
37  val mem = TLFuzzer(nOperations = 10)
38  val mmio = TLFuzzer(nOperations = 10)
39
40  lazy val module = new LazyModuleImp(this){
41
42  }
43}
44
45
46class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
47  private val cores = Seq.fill(NumCores)(LazyModule(new XSCore()))
48
49  // only mem and extDev visible externally
50  val dma = AXI4IdentityNode()
51  val extDev = AXI4IdentityNode()
52
53  // L2 to L3 network
54  // -------------------------------------------------
55  private val l3_xbar = TLXbar()
56
57  private val l3_banks = (0 until L3NBanks) map (i =>
58      LazyModule(new InclusiveCache(
59        CacheParameters(
60          level = 3,
61          ways = L3NWays,
62          sets = L3NSets,
63          blockBytes = L3BlockSize,
64          beatBytes = L2BusWidth / 8,
65          cacheName = s"L3_$i"
66        ),
67      InclusiveCacheMicroParameters(
68        writeBytes = 8
69      )
70    )))
71
72  cores.foreach(core => l3_xbar := TLBuffer() := DebugIdentityNode() := core.mem)
73
74  // DMA should not go to MMIO
75  val mmioRange = AddressSet(base = 0x0000000000L, mask = 0x007fffffffL)
76  // AXI4ToTL needs a TLError device to route error requests,
77  // add one here to make it happy.
78  val tlErrorParams = DevNullParams(
79    address = Seq(mmioRange),
80    maxAtomic = 8,
81    maxTransfer = 64)
82  val tlError = LazyModule(new TLError(params = tlErrorParams, beatBytes = L2BusWidth / 8))
83  private val tlError_xbar = TLXbar()
84  tlError_xbar :=
85    AXI4ToTL() :=
86    AXI4UserYanker(Some(1)) :=
87    AXI4Fragmenter() :=
88    AXI4IdIndexer(1) :=
89    dma
90  tlError.node := tlError_xbar
91
92  l3_xbar :=
93    TLBuffer() :=
94    DebugIdentityNode() :=
95    tlError_xbar
96
97  def bankFilter(bank: Int) = AddressSet(
98    base = bank * L3BlockSize,
99    mask = ~BigInt((L3NBanks -1) * L3BlockSize))
100
101  for(i <- 0 until L3NBanks) {
102    val filter = TLFilter(TLFilter.mSelectIntersect(bankFilter(i)))
103    l3_banks(i).node := TLBuffer() := DebugIdentityNode() := filter := l3_xbar
104  }
105
106
107  // L3 to memory network
108  // -------------------------------------------------
109  private val memory_xbar = TLXbar()
110
111  val mem = Seq.fill(L3NBanks)(AXI4IdentityNode())
112  for(i <- 0 until L3NBanks) {
113    mem(i) :=
114      AXI4UserYanker() :=
115      TLToAXI4() :=
116      TLWidthWidget(L3BusWidth / 8) :=
117      TLCacheCork() :=
118      l3_banks(i).node
119  }
120
121  private val mmioXbar = TLXbar()
122  private val clint = LazyModule(new TLTimer(
123    Seq(AddressSet(0x38000000L, 0x0000ffffL)),
124    sim = !env.FPGAPlatform
125  ))
126
127  cores.foreach(core =>
128    mmioXbar :=
129    TLBuffer() :=
130    DebugIdentityNode() :=
131    core.mmio
132  )
133
134  clint.node :=
135    mmioXbar
136
137  extDev :=
138    AXI4UserYanker() :=
139    TLToAXI4() :=
140    mmioXbar
141
142  lazy val module = new LazyModuleImp(this){
143    val io = IO(new Bundle{
144      val meip = Input(Bool())
145      val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
146    })
147    cores.foreach(core => {
148      core.module.io.externalInterrupt.mtip := clint.module.io.mtip
149      core.module.io.externalInterrupt.msip := clint.module.io.msip
150      core.module.io.externalInterrupt.meip := RegNext(RegNext(io.meip))
151    })
152    // do not let dma AXI signals optimized out
153    chisel3.dontTouch(dma.out.head._1)
154    chisel3.dontTouch(extDev.out.head._1)
155  }
156
157}
158