xref: /XiangShan/src/main/scala/system/SoC.scala (revision 1697a48eea0de9d216d8fa7537d967f8ef351e49) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41
42case class SoCParameters
43(
44  EnableILA: Boolean = false,
45  PAddrBits: Int = 48,
46  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
47  PMAConfigs: Seq[PMAConfigEntry] = Seq(
48    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
49    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
50    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
51    PMAConfigEntry(0x3A000000L, a = 1),
52    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
53    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
54    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
55    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
56    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
57    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
58    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
59    PMAConfigEntry(0)
60  ),
61  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
62  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
63  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
64  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
65  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
66  extIntrs: Int = 64,
67  L3NBanks: Int = 4,
68  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
69    name = "L3",
70    level = 3,
71    ways = 8,
72    sets = 2048 // 1MB per bank
73  )),
74  OpenLLCParamsOpt: Option[OpenLLCParam] = None,
75  XSTopPrefix: Option[String] = None,
76  NodeIDWidthList: Map[String, Int] = Map(
77    "B" -> 7,
78    "E.b" -> 11
79  ),
80  NumHart: Int = 64,
81  NumIRFiles: Int = 7,
82  NumIRSrc: Int = 256,
83  UseXSNoCTop: Boolean = false,
84  IMSICUseTL: Boolean = false,
85  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
86  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
87){
88  require(
89    L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,
90    "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined"
91  )
92  // L3 configurations
93  val L3InnerBusWidth = 256
94  val L3BlockSize = 64
95  // on chip network configurations
96  val L3OuterBusWidth = 256
97  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
98}
99
100trait HasSoCParameter {
101  implicit val p: Parameters
102
103  val soc = p(SoCParamsKey)
104  val debugOpts = p(DebugOptionsKey)
105  val tiles = p(XSTileKey)
106  val enableCHI = p(EnableCHI)
107  val issue = p(CHIIssue)
108
109  val NumCores = tiles.size
110  val EnableILA = soc.EnableILA
111
112  // Parameters for trace extension
113  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
114  val TraceCauseWidth             = tiles.head.XLEN
115  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
116  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
117  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
118  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
119  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
120  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
121
122  // L3 configurations
123  val L3InnerBusWidth = soc.L3InnerBusWidth
124  val L3BlockSize = soc.L3BlockSize
125  val L3NBanks = soc.L3NBanks
126
127  // on chip network configurations
128  val L3OuterBusWidth = soc.L3OuterBusWidth
129
130  val NrExtIntr = soc.extIntrs
131
132  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
133
134  val NumIRSrc = soc.NumIRSrc
135
136  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
137    soc.EnableCHIAsyncBridge else None
138  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
139}
140
141trait HasPeripheralRanges {
142  implicit val p: Parameters
143
144  private def soc = p(SoCParamsKey)
145  private def dm = p(DebugModuleKey)
146  private def pmParams = p(PMParameKey)
147
148  private def mmpma = pmParams.mmpma
149
150  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
151    "CLINT" -> soc.CLINTRange,
152    "BEU"   -> soc.BEURange,
153    "PLIC"  -> soc.PLICRange,
154    "PLL"   -> soc.PLLRange,
155    "UART"  -> soc.UARTLiteRange,
156    "DEBUG" -> dm.get.address,
157    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
158  ) ++ (
159    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
160      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
161    else
162      Map()
163  )
164
165  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
166    acc.flatMap(_.subtract(x))
167  }
168}
169
170class ILABundle extends Bundle {}
171
172
173abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
174  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
175  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
176  val l3_xbar = Option.when(!enableCHI)(TLXbar())
177  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
178
179  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
180}
181
182// We adapt the following three traits from rocket-chip.
183// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
184trait HaveSlaveAXI4Port {
185  this: BaseSoC =>
186
187  val idBits = 14
188
189  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
190    Seq(AXI4MasterParameters(
191      name = "dma",
192      id = IdRange(0, 1 << idBits)
193    ))
194  )))
195
196  if (l3_xbar.isDefined) {
197    val errorDevice = LazyModule(new TLError(
198      params = DevNullParams(
199        address = Seq(AddressSet(0x0, 0x7fffffffL)),
200        maxAtomic = 8,
201        maxTransfer = 64),
202      beatBytes = L3InnerBusWidth / 8
203    ))
204    errorDevice.node :=
205      l3_xbar.get :=
206      TLFIFOFixer() :=
207      TLWidthWidget(32) :=
208      AXI4ToTL() :=
209      AXI4UserYanker(Some(1)) :=
210      AXI4Fragmenter() :=
211      AXI4Buffer() :=
212      AXI4Buffer() :=
213      AXI4IdIndexer(1) :=
214      l3FrontendAXI4Node
215  }
216
217  val dma = InModuleBody {
218    l3FrontendAXI4Node.makeIOs()
219  }
220}
221
222trait HaveAXI4MemPort {
223  this: BaseSoC =>
224  val device = new MemoryDevice
225  // 48-bit physical address
226  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
227  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
228    AXI4SlavePortParameters(
229      slaves = Seq(
230        AXI4SlaveParameters(
231          address = memRange,
232          regionType = RegionType.UNCACHED,
233          executable = true,
234          supportsRead = TransferSizes(1, L3BlockSize),
235          supportsWrite = TransferSizes(1, L3BlockSize),
236          interleavedId = Some(0),
237          resources = device.reg("mem")
238        )
239      ),
240      beatBytes = L3OuterBusWidth / 8,
241      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
242    )
243  ))
244
245  val mem_xbar = TLXbar()
246  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
247  val axi4mem_node = AXI4IdentityNode()
248
249  if (enableCHI) {
250    axi4mem_node :=
251      soc_xbar.get
252  } else {
253    mem_xbar :=*
254      TLBuffer.chainNode(2) :=
255      TLCacheCork() :=
256      l3_mem_pmu :=
257      TLClientsMerger() :=
258      TLXbar() :=*
259      bankedNode.get
260
261    mem_xbar :=
262      TLWidthWidget(8) :=
263      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
264      peripheralXbar.get
265
266    axi4mem_node :=
267      TLToAXI4() :=
268      TLSourceShrinker(64) :=
269      TLWidthWidget(L3OuterBusWidth / 8) :=
270      TLBuffer.chainNode(2) :=
271      mem_xbar
272  }
273
274  memAXI4SlaveNode :=
275    AXI4Buffer() :=
276    AXI4Buffer() :=
277    AXI4Buffer() :=
278    AXI4IdIndexer(idBits = 14) :=
279    AXI4UserYanker() :=
280    AXI4Deinterleaver(L3BlockSize) :=
281    axi4mem_node
282
283  val memory = InModuleBody {
284    memAXI4SlaveNode.makeIOs()
285  }
286}
287
288trait HaveAXI4PeripheralPort { this: BaseSoC =>
289  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
290  val uartParams = AXI4SlaveParameters(
291    address = Seq(soc.UARTLiteRange),
292    regionType = RegionType.UNCACHED,
293    supportsRead = TransferSizes(1, 32),
294    supportsWrite = TransferSizes(1, 32),
295    resources = uartDevice.reg
296  )
297  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
298    Seq(AXI4SlaveParameters(
299      address = peripheralRange,
300      regionType = RegionType.UNCACHED,
301      supportsRead = TransferSizes(1, 32),
302      supportsWrite = TransferSizes(1, 32),
303      interleavedId = Some(0)
304    ), uartParams),
305    beatBytes = 8
306  )))
307
308  val axi4peripheral_node = AXI4IdentityNode()
309  val error_xbar = Option.when(enableCHI)(TLXbar())
310
311  peripheralNode :=
312    AXI4UserYanker() :=
313    AXI4IdIndexer(idBits = 2) :=
314    AXI4Buffer() :=
315    AXI4Buffer() :=
316    AXI4Buffer() :=
317    AXI4Buffer() :=
318    AXI4UserYanker() :=
319    // AXI4Deinterleaver(8) :=
320    axi4peripheral_node
321
322  if (enableCHI) {
323    val error = LazyModule(new TLError(
324      params = DevNullParams(
325        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
326        maxAtomic = 8,
327        maxTransfer = 64),
328      beatBytes = 8
329    ))
330    error.node := error_xbar.get
331    axi4peripheral_node :=
332      AXI4Deinterleaver(8) :=
333      TLToAXI4() :=
334      error_xbar.get :=
335      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
336      TLFIFOFixer() :=
337      TLWidthWidget(L3OuterBusWidth / 8) :=
338      AXI4ToTL() :=
339      AXI4UserYanker() :=
340      soc_xbar.get
341  } else {
342    axi4peripheral_node :=
343      AXI4Deinterleaver(8) :=
344      TLToAXI4() :=
345      TLBuffer.chainNode(3) :=
346      peripheralXbar.get
347  }
348
349  val peripheral = InModuleBody {
350    peripheralNode.makeIOs()
351  }
352
353}
354
355class MemMisc()(implicit p: Parameters) extends BaseSoC
356  with HaveAXI4MemPort
357  with PMAConst
358  with HaveAXI4PeripheralPort
359{
360
361  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
362  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
363
364  val l3_in = TLTempNode()
365  val l3_out = TLTempNode()
366
367  val device_xbar = Option.when(enableCHI)(TLXbar())
368  device_xbar.foreach(_ := error_xbar.get)
369
370  if (l3_banked_xbar.isDefined) {
371    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
372    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
373  }
374  bankedNode match {
375    case Some(bankBinder) =>
376      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
377    case None =>
378  }
379
380  if(soc.L3CacheParamsOpt.isEmpty){
381    l3_out :*= l3_in
382  }
383
384  if (!enableCHI) {
385    for (port <- peripheral_ports.get) {
386      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
387    }
388  }
389
390  core_to_l3_ports.foreach { case _ =>
391    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
392      l3_banked_xbar.get :=*
393        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
394        TLBuffer() :=
395        core_out
396    }
397  }
398
399  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
400  if (enableCHI) { clint.node := device_xbar.get }
401  else { clint.node := peripheralXbar.get }
402
403  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
404    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
405    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
406      val in = IO(Input(Vec(num, Bool())))
407      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
408    }
409    lazy val module = new IntSourceNodeToModuleImp(this)
410  }
411
412  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
413  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
414
415  plic.intnode := plicSource.sourceNode
416  if (enableCHI) { plic.node := device_xbar.get }
417  else { plic.node := peripheralXbar.get }
418
419  val pll_node = TLRegisterNode(
420    address = Seq(soc.PLLRange),
421    device = new SimpleDevice("pll_ctrl", Seq()),
422    beatBytes = 8,
423    concurrency = 1
424  )
425  if (enableCHI) { pll_node := device_xbar.get }
426  else { pll_node := peripheralXbar.get }
427
428  val debugModule = LazyModule(new DebugModule(NumCores)(p))
429  if (enableCHI) {
430    debugModule.debug.node := device_xbar.get
431    // TODO: l3_xbar
432    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
433      error_xbar.get := sb2tl.node
434    }
435  } else {
436    debugModule.debug.node := peripheralXbar.get
437    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
438      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
439    }
440  }
441
442  val pma = LazyModule(new TLPMA)
443  if (enableCHI) {
444    pma.node := TLBuffer.chainNode(4) := device_xbar.get
445  } else {
446    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
447  }
448
449  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
450
451    val debug_module_io = IO(new debugModule.DebugModuleIO)
452    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
453    val rtc_clock = IO(Input(Bool()))
454    val pll0_lock = IO(Input(Bool()))
455    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
456    val cacheable_check = IO(new TLPMAIO)
457    val clintTime = IO(Output(ValidIO(UInt(64.W))))
458
459    debugModule.module.io <> debug_module_io
460
461    // sync external interrupts
462    require(plicSource.module.in.length == ext_intrs.getWidth)
463    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
464      val ext_intr_sync = RegInit(0.U(3.W))
465      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
466      plic_in := ext_intr_sync(2)
467    }
468
469    pma.module.io <> cacheable_check
470
471    // positive edge sampling of the lower-speed rtc_clock
472    val rtcTick = RegInit(0.U(3.W))
473    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
474    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
475
476    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
477    val pll_lock = RegNext(next = pll0_lock, init = false.B)
478
479    clintTime := clint.module.io.time
480
481    pll0_ctrl <> VecInit(pll_ctrl_regs)
482
483    pll_node.regmap(
484      0x000 -> RegFieldGroup(
485        "Pll", Some("PLL ctrl regs"),
486        pll_ctrl_regs.zipWithIndex.map{
487          case (r, i) => RegField(32, r, RegFieldDesc(
488            s"PLL_ctrl_$i",
489            desc = s"PLL ctrl register #$i"
490          ))
491        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
492          "PLL_lock",
493          "PLL lock register"
494        ))
495      )
496    )
497  }
498
499  lazy val module = new SoCMiscImp(this)
500}
501
502class SoCMisc()(implicit p: Parameters) extends MemMisc
503  with HaveSlaveAXI4Port
504
505