xref: /XiangShan/src/main/scala/system/SoC.scala (revision 08373300e7dc356da02def6f35eae78b429872a7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO, AXI4MemEncrypt}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.debug.DebugModuleKey
25import freechips.rocketchip.devices.tilelink._
26import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
27import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
28import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.util.AsyncQueueParams
31import huancun._
32import top.BusPerfMonitor
33import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
34import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry, PMAConst}
35import xiangshan.{DebugOptionsKey, PMParameKey, XSTileKey}
36import coupledL2.{EnableCHI, L2Param}
37import coupledL2.tl2chi.CHIIssue
38import openLLC.OpenLLCParam
39
40case object SoCParamsKey extends Field[SoCParameters]
41case object CVMParamskey extends Field[CVMParameters]
42
43case class CVMParameters
44(
45  MEMENCRange: AddressSet = AddressSet(0x38030000L, 0xfff),
46  KeyIDBits: Int = 0,
47  MemencPipes: Int = 4,
48  HasMEMencryption: Boolean = false,
49  HasDelayNoencryption: Boolean = false, // Test specific
50)
51
52case class SoCParameters
53(
54  EnableILA: Boolean = false,
55  PAddrBits: Int = 48,
56  PmemRanges: Seq[MemoryRange] = Seq(MemoryRange(0x80000000L, 0x80000000000L)),
57  PMAConfigs: Seq[PMAConfigEntry] = Seq(
58    PMAConfigEntry(0x0L, range = 0x1000000000000L, a = 3),
59    PMAConfigEntry(0x80000000000L, c = true, atomic = true, a = 1, x = true, w = true, r = true),
60    PMAConfigEntry(0x80000000L, a = 1, w = true, r = true),
61    PMAConfigEntry(0x3A000000L, a = 1),
62    PMAConfigEntry(0x39002000L, a = 1, w = true, r = true),
63    PMAConfigEntry(0x39000000L, a = 1, w = true, r = true),
64    PMAConfigEntry(0x38022000L, a = 1, w = true, r = true),
65    PMAConfigEntry(0x38021000L, a = 1, x = true, w = true, r = true),
66    PMAConfigEntry(0x38020000L, a = 1, w = true, r = true),
67    PMAConfigEntry(0x30050000L, a = 1, w = true, r = true), // FIXME: GPU space is cacheable?
68    PMAConfigEntry(0x30010000L, a = 1, w = true, r = true),
69    PMAConfigEntry(0x20000000L, a = 1, x = true, w = true, r = true),
70    PMAConfigEntry(0x10000000L, a = 1, w = true, r = true),
71    PMAConfigEntry(0)
72  ),
73  CLINTRange: AddressSet = AddressSet(0x38000000L, CLINTConsts.size - 1),
74  BEURange: AddressSet = AddressSet(0x38010000L, 0xfff),
75  PLICRange: AddressSet = AddressSet(0x3c000000L, PLICConsts.size(PLICConsts.maxMaxHarts) - 1),
76  PLLRange: AddressSet = AddressSet(0x3a000000L, 0xfff),
77  UARTLiteForDTS: Boolean = true, // should be false in SimMMIO
78  extIntrs: Int = 64,
79  L3NBanks: Int = 4,
80  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
81    name = "L3",
82    level = 3,
83    ways = 8,
84    sets = 2048 // 1MB per bank
85  )),
86  OpenLLCParamsOpt: Option[OpenLLCParam] = None,
87  XSTopPrefix: Option[String] = None,
88  NodeIDWidthList: Map[String, Int] = Map(
89    "B" -> 7,
90    "C" -> 9,
91    "E.b" -> 11
92  ),
93  NumHart: Int = 64,
94  NumIRFiles: Int = 7,
95  NumIRSrc: Int = 256,
96  UseXSNoCTop: Boolean = false,
97  UseXSNoCDiffTop: Boolean = false,
98  UseXSTileDiffTop: Boolean = false,
99  IMSICUseTL: Boolean = false,
100  SeperateDMBus: Boolean = false,
101  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 16, sync = 3, safe = false)),
102  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false)),
103  EnableDMAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
104){
105  require(
106    L3CacheParamsOpt.isDefined ^ OpenLLCParamsOpt.isDefined || L3CacheParamsOpt.isEmpty && OpenLLCParamsOpt.isEmpty,
107    "Atmost one of L3CacheParamsOpt and OpenLLCParamsOpt should be defined"
108  )
109  // L3 configurations
110  val L3InnerBusWidth = 256
111  val L3BlockSize = 64
112  // on chip network configurations
113  val L3OuterBusWidth = 256
114  val UARTLiteRange = AddressSet(0x40600000, if (UARTLiteForDTS) 0x3f else 0xf)
115}
116
117trait HasSoCParameter {
118  implicit val p: Parameters
119
120  val soc = p(SoCParamsKey)
121  val cvm = p(CVMParamskey)
122  val debugOpts = p(DebugOptionsKey)
123  val tiles = p(XSTileKey)
124  val enableCHI = p(EnableCHI)
125  val issue = p(CHIIssue)
126
127  val NumCores = tiles.size
128  val EnableILA = soc.EnableILA
129
130  // Parameters for trace extension
131  val TraceTraceGroupNum          = tiles.head.traceParams.TraceGroupNum
132  val TraceCauseWidth             = tiles.head.XLEN
133  val TraceTvalWidth              = tiles.head.traceParams.IaddrWidth
134  val TracePrivWidth              = tiles.head.traceParams.PrivWidth
135  val TraceIaddrWidth             = tiles.head.traceParams.IaddrWidth
136  val TraceItypeWidth             = tiles.head.traceParams.ItypeWidth
137  val TraceIretireWidthCompressed = log2Up(tiles.head.RenameWidth * tiles.head.CommitWidth * 2)
138  val TraceIlastsizeWidth         = tiles.head.traceParams.IlastsizeWidth
139
140  // L3 configurations
141  val L3InnerBusWidth = soc.L3InnerBusWidth
142  val L3BlockSize = soc.L3BlockSize
143  val L3NBanks = soc.L3NBanks
144
145  // on chip network configurations
146  val L3OuterBusWidth = soc.L3OuterBusWidth
147
148  val NrExtIntr = soc.extIntrs
149
150  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
151
152  val NumIRSrc = soc.NumIRSrc
153
154  val SeperateDMBus = soc.SeperateDMBus
155
156  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
157    soc.EnableCHIAsyncBridge else None
158  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
159  val EnableDMAsyncBridge = if (SeperateDMBus && soc.EnableDMAsyncBridge.isDefined)
160    soc.EnableDMAsyncBridge else None
161
162  def HasMEMencryption = cvm.HasMEMencryption
163  require((cvm.HasMEMencryption && (cvm.KeyIDBits > 0)) || (!cvm.HasMEMencryption && (cvm.KeyIDBits == 0)),
164    "HasMEMencryption most set with KeyIDBits > 0")
165}
166
167trait HasPeripheralRanges {
168  implicit val p: Parameters
169
170  private def cvm = p(CVMParamskey)
171  private def soc = p(SoCParamsKey)
172  private def dm = p(DebugModuleKey)
173  private def pmParams = p(PMParameKey)
174
175  private def mmpma = pmParams.mmpma
176
177  def onChipPeripheralRanges: Map[String, AddressSet] = Map(
178    "CLINT" -> soc.CLINTRange,
179    "BEU"   -> soc.BEURange,
180    "PLIC"  -> soc.PLICRange,
181    "PLL"   -> soc.PLLRange,
182    "UART"  -> soc.UARTLiteRange,
183    "DEBUG" -> dm.get.address,
184    "MMPMA" -> AddressSet(mmpma.address, mmpma.mask)
185  ) ++ (
186    if (soc.L3CacheParamsOpt.map(_.ctrl.isDefined).getOrElse(false))
187      Map("L3CTL" -> AddressSet(soc.L3CacheParamsOpt.get.ctrl.get.address, 0xffff))
188    else
189      Map()
190  ) ++ (
191    if (cvm.HasMEMencryption)
192      Map("MEMENC"  -> cvm.MEMENCRange)
193    else
194      Map()
195  )
196
197  def peripheralRange = onChipPeripheralRanges.values.foldLeft(Seq(AddressSet(0x0, 0x7fffffffL))) { (acc, x) =>
198    acc.flatMap(_.subtract(x))
199  }
200}
201
202class ILABundle extends Bundle {}
203
204
205abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter with HasPeripheralRanges {
206  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
207  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
208  val l3_xbar = Option.when(!enableCHI)(TLXbar())
209  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
210
211  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
212}
213
214// We adapt the following three traits from rocket-chip.
215// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
216trait HaveSlaveAXI4Port {
217  this: BaseSoC =>
218
219  val idBits = 14
220
221  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
222    Seq(AXI4MasterParameters(
223      name = "dma",
224      id = IdRange(0, 1 << idBits)
225    ))
226  )))
227
228  if (l3_xbar.isDefined) {
229    val errorDevice = LazyModule(new TLError(
230      params = DevNullParams(
231        address = Seq(AddressSet(0x0, 0x7fffffffL)),
232        maxAtomic = 8,
233        maxTransfer = 64),
234      beatBytes = L3InnerBusWidth / 8
235    ))
236    errorDevice.node :=
237      l3_xbar.get :=
238      TLFIFOFixer() :=
239      TLWidthWidget(32) :=
240      AXI4ToTL() :=
241      AXI4UserYanker(Some(1)) :=
242      AXI4Fragmenter() :=
243      AXI4Buffer() :=
244      AXI4Buffer() :=
245      AXI4IdIndexer(1) :=
246      l3FrontendAXI4Node
247  }
248
249  val dma = InModuleBody {
250    l3FrontendAXI4Node.makeIOs()
251  }
252}
253
254trait HaveAXI4MemPort {
255  this: BaseSoC =>
256  val device = new MemoryDevice
257  // 48-bit physical address
258  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
259  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
260    AXI4SlavePortParameters(
261      slaves = Seq(
262        AXI4SlaveParameters(
263          address = memRange,
264          regionType = RegionType.UNCACHED,
265          executable = true,
266          supportsRead = TransferSizes(1, L3BlockSize),
267          supportsWrite = TransferSizes(1, L3BlockSize),
268          interleavedId = Some(0),
269          resources = device.reg("mem")
270        )
271      ),
272      beatBytes = L3OuterBusWidth / 8,
273      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
274    )
275  ))
276
277  val mem_xbar = TLXbar()
278  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
279  val axi4mem_node = AXI4IdentityNode()
280
281  if (enableCHI) {
282    axi4mem_node :=
283      soc_xbar.get
284  } else {
285    mem_xbar :=*
286      TLBuffer.chainNode(2) :=
287      TLCacheCork() :=
288      l3_mem_pmu :=
289      TLClientsMerger() :=
290      TLXbar() :=*
291      bankedNode.get
292
293    mem_xbar :=
294      TLWidthWidget(8) :=
295      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
296      peripheralXbar.get
297
298    axi4mem_node :=
299      TLToAXI4() :=
300      TLSourceShrinker(64) :=
301      TLWidthWidget(L3OuterBusWidth / 8) :=
302      TLBuffer.chainNode(2) :=
303      mem_xbar
304  }
305  val axi4memencrpty = Option.when(HasMEMencryption)(LazyModule(new AXI4MemEncrypt(cvm.MEMENCRange)))
306  if (HasMEMencryption) {
307    memAXI4SlaveNode :=
308      AXI4Buffer() :=
309      AXI4Buffer() :=
310      AXI4Buffer() :=
311      AXI4IdIndexer(idBits = 14) :=
312      AXI4UserYanker() :=
313      axi4memencrpty.get.node
314
315    axi4memencrpty.get.node :=
316      AXI4Deinterleaver(L3BlockSize) :=
317      axi4mem_node
318  } else {
319    memAXI4SlaveNode :=
320      AXI4Buffer() :=
321      AXI4Buffer() :=
322      AXI4Buffer() :=
323      AXI4IdIndexer(idBits = 14) :=
324      AXI4UserYanker() :=
325      AXI4Deinterleaver(L3BlockSize) :=
326      axi4mem_node
327  }
328
329
330  val memory = InModuleBody {
331    memAXI4SlaveNode.makeIOs()
332  }
333}
334
335trait HaveAXI4PeripheralPort { this: BaseSoC =>
336  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
337  val uartParams = AXI4SlaveParameters(
338    address = Seq(soc.UARTLiteRange),
339    regionType = RegionType.UNCACHED,
340    supportsRead = TransferSizes(1, 32),
341    supportsWrite = TransferSizes(1, 32),
342    resources = uartDevice.reg
343  )
344  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
345    Seq(AXI4SlaveParameters(
346      address = peripheralRange,
347      regionType = RegionType.UNCACHED,
348      supportsRead = TransferSizes(1, 32),
349      supportsWrite = TransferSizes(1, 32),
350      interleavedId = Some(0)
351    ), uartParams),
352    beatBytes = 8
353  )))
354
355  val axi4peripheral_node = AXI4IdentityNode()
356  val error_xbar = Option.when(enableCHI)(TLXbar())
357
358  peripheralNode :=
359    AXI4UserYanker() :=
360    AXI4IdIndexer(idBits = 2) :=
361    AXI4Buffer() :=
362    AXI4Buffer() :=
363    AXI4Buffer() :=
364    AXI4Buffer() :=
365    AXI4UserYanker() :=
366    // AXI4Deinterleaver(8) :=
367    axi4peripheral_node
368
369  if (enableCHI) {
370    val error = LazyModule(new TLError(
371      params = DevNullParams(
372        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
373        maxAtomic = 8,
374        maxTransfer = 64),
375      beatBytes = 8
376    ))
377    error.node := error_xbar.get
378    axi4peripheral_node :=
379      AXI4Deinterleaver(8) :=
380      TLToAXI4() :=
381      error_xbar.get :=
382      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
383      TLFIFOFixer() :=
384      TLWidthWidget(L3OuterBusWidth / 8) :=
385      AXI4ToTL() :=
386      AXI4UserYanker() :=
387      soc_xbar.get
388  } else {
389    axi4peripheral_node :=
390      AXI4Deinterleaver(8) :=
391      TLToAXI4() :=
392      TLBuffer.chainNode(3) :=
393      peripheralXbar.get
394  }
395
396  val peripheral = InModuleBody {
397    peripheralNode.makeIOs()
398  }
399
400}
401
402class MemMisc()(implicit p: Parameters) extends BaseSoC
403  with HaveAXI4MemPort
404  with PMAConst
405  with HaveAXI4PeripheralPort
406{
407
408  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
409  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
410
411  val l3_in = TLTempNode()
412  val l3_out = TLTempNode()
413
414  val device_xbar = Option.when(enableCHI)(TLXbar())
415  device_xbar.foreach(_ := error_xbar.get)
416
417  if (l3_banked_xbar.isDefined) {
418    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
419    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
420  }
421  bankedNode match {
422    case Some(bankBinder) =>
423      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
424    case None =>
425  }
426
427  if(soc.L3CacheParamsOpt.isEmpty){
428    l3_out :*= l3_in
429  }
430
431  if (!enableCHI) {
432    for (port <- peripheral_ports.get) {
433      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
434    }
435  }
436
437  core_to_l3_ports.foreach { case _ =>
438    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
439      l3_banked_xbar.get :=*
440        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
441        TLBuffer() :=
442        core_out
443    }
444  }
445
446  val clint = LazyModule(new CLINT(CLINTParams(soc.CLINTRange.base), 8))
447  if (enableCHI) { clint.node := device_xbar.get }
448  else { clint.node := peripheralXbar.get }
449
450  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
451    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
452    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
453      val in = IO(Input(Vec(num, Bool())))
454      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
455    }
456    lazy val module = new IntSourceNodeToModuleImp(this)
457  }
458
459  val plic = LazyModule(new TLPLIC(PLICParams(soc.PLICRange.base), 8))
460  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
461
462  plic.intnode := plicSource.sourceNode
463  if (enableCHI) { plic.node := device_xbar.get }
464  else { plic.node := peripheralXbar.get }
465
466  val pll_node = TLRegisterNode(
467    address = Seq(soc.PLLRange),
468    device = new SimpleDevice("pll_ctrl", Seq()),
469    beatBytes = 8,
470    concurrency = 1
471  )
472  if (enableCHI) { pll_node := device_xbar.get }
473  else { pll_node := peripheralXbar.get }
474
475  val debugModule = LazyModule(new DebugModule(NumCores)(p))
476  val debugModuleXbarOpt = Option.when(SeperateDMBus)(TLXbar())
477  if (enableCHI) {
478    if (SeperateDMBus) {
479      debugModule.debug.node := debugModuleXbarOpt.get
480    } else {
481      debugModule.debug.node := device_xbar.get
482    }
483    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
484      error_xbar.get := sb2tl.node
485    }
486  } else {
487    if (SeperateDMBus) {
488      debugModule.debug.node := debugModuleXbarOpt.get
489    } else {
490      debugModule.debug.node := peripheralXbar.get
491    }
492    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
493      l3_xbar.get := TLBuffer() := TLWidthWidget(1) := sb2tl.node
494    }
495  }
496
497  val pma = LazyModule(new TLPMA)
498  if (enableCHI) {
499    pma.node := TLBuffer.chainNode(4) := device_xbar.get
500    if (HasMEMencryption) {
501      axi4memencrpty.get.ctrl_node := TLToAPB() := device_xbar.get
502    }
503  } else {
504    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
505    if (HasMEMencryption) {
506      axi4memencrpty.get.ctrl_node := TLToAPB() := peripheralXbar.get
507    }
508  }
509
510  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
511
512    val debug_module_io = IO(new debugModule.DebugModuleIO)
513    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
514    val rtc_clock = IO(Input(Bool()))
515    val pll0_lock = IO(Input(Bool()))
516    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
517    val cacheable_check = IO(new TLPMAIO)
518    val clintTime = IO(Output(ValidIO(UInt(64.W))))
519
520    debugModule.module.io <> debug_module_io
521
522    // sync external interrupts
523    require(plicSource.module.in.length == ext_intrs.getWidth)
524    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
525      val ext_intr_sync = RegInit(0.U(3.W))
526      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
527      plic_in := ext_intr_sync(2)
528    }
529
530    pma.module.io <> cacheable_check
531
532    if (HasMEMencryption) {
533      val cnt = Counter(true.B, 8)._1
534      axi4memencrpty.get.module.io.random_val := axi4memencrpty.get.module.io.random_req && cnt(2).asBool
535      axi4memencrpty.get.module.io.random_data := cnt(0).asBool
536    }
537    // positive edge sampling of the lower-speed rtc_clock
538    val rtcTick = RegInit(0.U(3.W))
539    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
540    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
541
542    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
543    val pll_lock = RegNext(next = pll0_lock, init = false.B)
544
545    clintTime := clint.module.io.time
546
547    pll0_ctrl <> VecInit(pll_ctrl_regs)
548
549    pll_node.regmap(
550      0x000 -> RegFieldGroup(
551        "Pll", Some("PLL ctrl regs"),
552        pll_ctrl_regs.zipWithIndex.map{
553          case (r, i) => RegField(32, r, RegFieldDesc(
554            s"PLL_ctrl_$i",
555            desc = s"PLL ctrl register #$i"
556          ))
557        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
558          "PLL_lock",
559          "PLL lock register"
560        ))
561      )
562    )
563  }
564
565  lazy val module = new SoCMiscImp(this)
566}
567
568class SoCMisc()(implicit p: Parameters) extends MemMisc
569  with HaveSlaveAXI4Port
570
571