xref: /XiangShan/src/main/scala/device/TLTimer.scala (revision 367512b707c976b7ff3fa2e0a4cf1b35a5c1d3c2) 
1package device
2
3import chisel3._
4import chisel3.util._
5import freechips.rocketchip.tilelink._
6import chipsalliance.rocketchip.config._
7import freechips.rocketchip.diplomacy._
8import freechips.rocketchip.regmapper.RegField
9import utils.{HasTLDump, XSDebug}
10import xiangshan.HasXSLog
11
12class TLTimer(address: Seq[AddressSet], sim: Boolean)(implicit p: Parameters) extends LazyModule {
13
14  val device = new SimpleDevice("clint", Seq("XiangShan", "clint"))
15  val node = TLRegisterNode(address, device, beatBytes = 8)
16  val NumCores = top.Parameters.get.socParameters.NumCores
17
18  lazy val module = new LazyModuleImp(this) with HasXSLog with HasTLDump{
19    val io = IO(new Bundle() {
20      val mtip = Output(Vec(NumCores, Bool()))
21      val msip = Output(Vec(NumCores, Bool()))
22    })
23
24    val mtime = RegInit(0.U(64.W))  // unit: us
25    val mtimecmp = Seq.fill(NumCores)(RegInit(0.U(64.W)))
26    val msip = Seq.fill(NumCores)(RegInit(0.U(32.W)))
27
28    val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 100)
29    val freq = RegInit(clk.U(16.W))
30    val inc = RegInit(1.U(16.W))
31
32    val cnt = RegInit(0.U(16.W))
33    val nextCnt = cnt + 1.U
34    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
35    val tick = (nextCnt === freq)
36    when (tick) { mtime := mtime + inc }
37
38    var clintMapping = Seq(
39      0x8000 -> RegField.bytes(freq),
40      0x8008 -> RegField.bytes(inc),
41      0xbff8 -> RegField.bytes(mtime))
42
43    for (i <- 0 until NumCores) {
44      clintMapping = clintMapping ++ Seq(
45        0x0000 + i*4 -> RegField.bytes(msip(i)),
46        0x4000 + i*8 -> RegField.bytes(mtimecmp(i))
47      )
48    }
49
50    node.regmap( mapping = clintMapping:_* )
51
52    val in = node.in.head._1
53    when(in.a.valid){
54      XSDebug("[A] channel valid ready=%d ", in.a.ready)
55      in.a.bits.dump
56    }
57
58//    val gtime = GTimer()
59//    printf(p"[$gtime][Timer] mtime=$mtime cnt=$cnt freq=$freq\n")
60
61    for (i <- 0 until NumCores) {
62      io.mtip(i) := RegNext(mtime >= mtimecmp(i))
63      io.msip(i) := RegNext(msip(i) =/= 0.U)
64    }
65  }
66}
67