1package device 2 3import chisel3._ 4import chisel3.util._ 5import bus.axi4._ 6import chipsalliance.rocketchip.config.Parameters 7import freechips.rocketchip.diplomacy.AddressSet 8import utils._ 9 10class UARTIO extends Bundle { 11 val out = new Bundle { 12 val valid = Output(Bool()) 13 val ch = Output(UInt(8.W)) 14 } 15 val in = new Bundle { 16 val valid = Output(Bool()) 17 val ch = Input(UInt(8.W)) 18 } 19} 20 21class AXI4UART 22( 23 address: Seq[AddressSet] 24)(implicit p: Parameters) 25 extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO) 26{ 27 override lazy val module = new AXI4SlaveModuleImp[UARTIO](this){ 28 val rxfifo = RegInit(0.U(32.W)) 29 val txfifo = Reg(UInt(32.W)) 30 val stat = RegInit(1.U(32.W)) 31 val ctrl = RegInit(0.U(32.W)) 32 33 io.extra.get.out.valid := (waddr(3,0) === 4.U && in.w.fire()) 34 io.extra.get.out.ch := in.w.bits.data(7,0) 35 io.extra.get.in.valid := (raddr(3,0) === 0.U && in.r.fire()) 36 37 val mapping = Map( 38 RegMap(0x0, io.extra.get.in.ch, RegMap.Unwritable), 39 RegMap(0x4, txfifo), 40 RegMap(0x8, stat), 41 RegMap(0xc, ctrl) 42 ) 43 44 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 45 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb >> waddr(2,0)) 46 ) 47 } 48} 49