1// See LICENSE.SiFive for license details. 2 3package device 4 5import chisel3._ 6import chisel3.util._ 7 8import bus.axi4._ 9import utils._ 10 11class AXI4Timer extends Module { 12 val io = IO(new Bundle{ 13 val in = Flipped(new AXI4Lite) 14 }) 15 16 val in = io.in 17 18 val clk = 50000 // 50MHz / 1000 19 val tick = Counter(true.B, clk)._2 20 val ms = Counter(tick, 0x40000000)._1 21 22 // deal with non-rready master 23 val rInflight = BoolStopWatch(in.ar.fire(), in.r.fire(), startHighPriority = true) 24 in.ar.ready := in.r.ready || !rInflight 25 in.r.valid := rInflight 26 in.r.bits.data := ms 27 in.r.bits.resp := AXI4Parameters.RESP_OKAY 28 29 // deal with non-bready master 30 val wInflight = BoolStopWatch(in.aw.fire(), in.b.fire(), startHighPriority = true) 31 in.aw.ready := in.w.valid && (in.b.ready || !wInflight) 32 in.w.ready := in.aw.valid && (in.b.ready || !wInflight) 33 in.b.valid := wInflight 34 in.b.bits.resp := AXI4Parameters.RESP_OKAY 35} 36