1package device 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.axi4._ 7import utils._ 8 9class TimerIO extends Bundle { 10 val mtip = Output(Bool()) 11} 12 13class AXI4Timer(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new TimerIO) { 14 val mtime = RegInit(0.U(64.W)) // unit: ms 15 val mtimecmp = RegInit(0.U(64.W)) 16 17 val clk = (if (!sim) 40000 /* 40MHz / 1000 */ else 10000) 18 val tick = Counter(true.B, clk)._2 19 when (tick) { mtime := mtime + 1.U } 20 21 val mapping = Map( 22 RegMap(0x0, mtime), 23 RegMap(0x8, mtimecmp) 24 ) 25 26 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 27 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb)) 28 29 io.extra.get.mtip := RegNext(mtime >= mtimecmp) 30} 31