xref: /XiangShan/src/main/scala/device/AXI4Flash.scala (revision ab3aa7eedc9c70d560572701ea30e863011452a8) 
1package device
2
3import chisel3._
4import chisel3.util._
5import chipsalliance.rocketchip.config.Parameters
6import freechips.rocketchip.diplomacy.AddressSet
7import utils._
8
9class AXI4Flash
10(
11  address: Seq[AddressSet]
12)(implicit p: Parameters)
13  extends AXI4SlaveModule(address, executable = false)
14{
15
16  override lazy val module = new AXI4SlaveModuleImp(this){
17    val jmpToDramInstr1 = "h0010029b".U  // addiw t0,zero,1
18    val jmpToDramInstr2 = "h01f29293".U  // slli  t0,t0,0x1f
19    val jmpToDramInstr3 = "h00028067".U  // jr t0
20
21    val mapping = Map(
22      RegMap(0x0, jmpToDramInstr1, RegMap.Unwritable),
23      RegMap(0x4, jmpToDramInstr2, RegMap.Unwritable),
24      RegMap(0x8, jmpToDramInstr3, RegMap.Unwritable)
25    )
26    def getOffset(addr: UInt) = addr(12,0)
27
28    val rdata = Wire(UInt(64.W))
29    RegMap.generate(mapping, getOffset(raddr), rdata,
30      getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))
31
32    in.r.bits.data := Fill(2, rdata(31,0))
33  }
34}
35