xref: /XiangShan/src/main/resources/config/Default.yml (revision dd3d70bad8def5b15d6c20ec5888b367b0575198) 
1PmemRanges:
2  - { lower: 0x80000000, upper: 0x80000000000 }
3
4PMAConfigs:
5  - { base_addr: 0x0, range: 0x1000000000000, a: 3 }
6  - { base_addr: 0x80000000000, c: true, atomic: true, a: 1, x: true, w: true, r: true }
7  - { base_addr: 0x80000000, a: 1, w: true, r: true }
8  - { base_addr: 0x3A000000, a: 1 }
9  - { base_addr: 0x39002000, a: 1, w: true, r: true }
10  - { base_addr: 0x39000000, a: 1, w: true, r: true }
11  - { base_addr: 0x38022000, a: 1, w: true, r: true }
12  - { base_addr: 0x38021000, a: 1, x: true, w: true, r: true }
13  - { base_addr: 0x30010000, a: 1, w: true, r: true }
14  - { base_addr: 0x20000000, a: 1, x: true, w: true, r: true }
15  - { base_addr: 0x10000000, a: 1, w: true, r: true }
16  - { base_addr: 0 }
17
18EnableCHIAsyncBridge: true
19
20L2CacheConfig: { size: 1 MB, ways: 8, inclusive: true, banks: 4, tp: true }
21
22L3CacheConfig: { size: 16 MB, ways: 16, inclusive: false, banks: 4 }
23
24DebugModuleBaseAddr: 0x38020000
25
26WFIResume: true
27
28SeperateDM: false
29
30SeperateTLBus: false
31
32SeperateTLBusRanges:
33  - { base: 0x38020000, mask: 0xFFF } # Default Debug Module Address
34
35IMSICBusType: AXI
36
37IMSICParams:
38  imsicIntSrcWidth: 8
39  mAddr: 0x3A800000
40  sgAddr: 0x3B000000
41  geilen: 5
42  vgeinWidth: 6
43  iselectWidth: 12
44  EnableImsicAsyncBridge: true
45  HasTEEIMSIC: false
46