1PmemRanges: 2 - { lower: 0x80000000, upper: 0x80000000000 } 3 4PMAConfigs: 5 - { base_addr: 0x0, range: 0x1000000000000, a: 3 } 6 - { base_addr: 0x80000000000, c: true, atomic: true, a: 1, x: true, w: true, r: true } 7 - { base_addr: 0x80000000, a: 1, w: true, r: true } 8 - { base_addr: 0x3A000000, a: 1 } 9 - { base_addr: 0x39002000, a: 1, w: true, r: true } 10 - { base_addr: 0x39000000, a: 1, w: true, r: true } 11 - { base_addr: 0x38022000, a: 1, w: true, r: true } 12 - { base_addr: 0x38021000, a: 1, x: true, w: true, r: true } 13 - { base_addr: 0x30010000, a: 1, w: true, r: true } 14 - { base_addr: 0x20000000, a: 1, x: true, w: true, r: true } 15 - { base_addr: 0x10000000, a: 1, w: true, r: true } 16 - { base_addr: 0 } 17 18EnableCHIAsyncBridge: true 19 20L2CacheConfig: { size: 1 MB, ways: 8, inclusive: true, banks: 4, tp: true } 21 22L3CacheConfig: { size: 16 MB, ways: 16, inclusive: false, banks: 4 } 23 24HartIDBits: 6 25 26DebugAttachProtocals: [JTAG] 27 28DebugModuleParams: 29 nAbstractDataWords: 2 30 maxSupportedSBAccess: 64 31 hasBusMaster: true 32 baseAddress: 0x38020000 33 nScratch: 2 34 crossingHasSafeReset: false 35 hasHartResets: true 36 37WFIResume: true 38 39SeperateDM: false 40 41SeperateTLBus: false 42 43SeperateTLBusRanges: 44 - { base: 0x38020000, mask: 0xFFF } # Default Debug Module Address 45 46EnableSeperateTLBusAsyncBridge: true 47 48IMSICBusType: AXI 49 50IMSICParams: 51 imsicIntSrcWidth: 8 52 mAddr: 0x3A800000 53 sgAddr: 0x3B000000 54 geilen: 5 55 vgeinWidth: 6 56 iselectWidth: 12 57 EnableImsicAsyncBridge: true 58 HasTEEIMSIC: false 59 60CHIIssue: E.b 61 62WFIClockGate: false 63 64EnablePowerDown: false 65 66XSTopPrefix: "" 67 68EnableDFX: true 69 70EnableSramCtl: false 71 72EnableCHINS: false 73