xref: /XiangShan/build.sc (revision 7a2fc509e2d355879c4db3dc3f17a6ccacd3d09e) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17import os.Path
18import mill._
19import scalalib._
20import publish._
21import coursier.maven.MavenRepository
22import $file.`rocket-chip`.common
23import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
24import $file.`rocket-chip`.hardfloat.build
25
26object ivys {
27  val sv = "2.12.13"
28  val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
29  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
30  val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.3.2"
31  val chiselCirct = ivy"com.sifive::chisel-circt:0.4.0"
32  val scalatest = ivy"org.scalatest::scalatest:3.2.2"
33  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
34}
35
36trait XSModule extends ScalaModule with PublishModule {
37
38  // override this to use chisel from source
39  def chiselOpt: Option[PublishModule] = None
40
41  override def scalaVersion = ivys.sv
42
43  override def compileIvyDeps = Agg(ivys.macroParadise)
44
45  override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.chisel3Plugin)
46
47  override def scalacOptions = Seq("-Xsource:2.11")
48
49  override def ivyDeps = (if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]) ++ Agg(ivys.chiselCirct)
50
51  override def moduleDeps = Seq() ++ chiselOpt
52
53  def publishVersion = "0.0.1"
54
55  // TODO: fix this
56  def pomSettings = PomSettings(
57    description = "XiangShan",
58    organization = "",
59    url = "https://github.com/OpenXiangShan/XiangShan",
60    licenses = Seq(License.`Apache-2.0`),
61    versionControl = VersionControl.github("OpenXiangShan", "XiangShan"),
62    developers = Seq.empty
63  )
64}
65
66object rocketchip extends `rocket-chip`.common.CommonRocketChip {
67
68  val rcPath = os.pwd / "rocket-chip"
69
70  override def scalaVersion = ivys.sv
71
72  override def scalacOptions = Seq("-Xsource:2.11")
73
74  override def millSourcePath = rcPath
75
76  object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
77    override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
78
79    override def scalaVersion = T {
80      rocketchip.scalaVersion()
81    }
82
83    override def pomSettings = T {
84      rocketchip.pomSettings()
85    }
86
87    override def publishVersion = T {
88      rocketchip.publishVersion()
89    }
90  }
91
92  object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
93    override def millSourcePath = rcPath / "hardfloat"
94
95    override def scalaVersion = T {
96      rocketchip.scalaVersion()
97    }
98
99    def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
100      common.getVersion("chisel3")
101    ) else Agg.empty[Dep]
102  }
103
104  def hardfloatModule = hardfloatRocket
105
106  def configModule = configRocket
107
108}
109
110object huancun extends XSModule with SbtModule {
111
112  override def millSourcePath = os.pwd / "huancun"
113
114  override def moduleDeps = super.moduleDeps ++ Seq(
115    rocketchip
116  )
117}
118
119object difftest extends XSModule with SbtModule {
120  override def millSourcePath = os.pwd / "difftest"
121}
122
123object fudian extends XSModule with SbtModule
124
125// extends this trait to use XiangShan in other projects
126trait CommonXiangShan extends XSModule with SbtModule { m =>
127
128  // module deps
129  def rocketModule: PublishModule
130  def difftestModule: PublishModule
131  def huancunModule: PublishModule
132  def fudianModule: PublishModule
133
134  override def millSourcePath = os.pwd
135
136  override def forkArgs = Seq("-Xmx64G", "-Xss256m")
137
138  override def ivyDeps = super.ivyDeps() ++ Seq(ivys.chiseltest)
139
140  override def moduleDeps = super.moduleDeps ++ Seq(
141    rocketModule,
142    difftestModule,
143    huancunModule,
144    fudianModule
145  )
146
147  object test extends Tests with TestModule.ScalaTest {
148
149    override def forkArgs = m.forkArgs
150
151    override def ivyDeps = super.ivyDeps() ++ Agg(
152      ivys.scalatest
153    )
154
155  }
156
157}
158
159object XiangShan extends CommonXiangShan {
160  override def rocketModule = rocketchip
161  override def difftestModule = difftest
162  override def huancunModule = huancun
163  override def fudianModule = fudian
164}
165