xref: /XiangShan/README.md (revision c6d439803a044ea209139672b25e35fe8d7f4aa0)
1# XiangShan
2
3XiangShan is an open-source high-performance RISC-V processor.
4
5NOTE: XiangShan has not been officially released to the public open-source community.
6License and docs to be added later.
7
8Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
9
10## Prepare environment
11
12* Set environment variable `NEMU_HOME` to the **absolute path** of the [NEMU project](https://github.com/OpenXiangShan/NEMU).
13* Set environment variable `NOOP_HOME` to the **absolute path** of the XiangShan project.
14* Set environment variable `AM_HOME` to the **absolute path** of the [AM project](https://github.com/OpenXiangShan/nexus-am).
15* Install `mill`. Refer to [the Manual section in this guide](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation).
16* Run `make init` to initialize submodules.
17
18## Run simulation
19
20* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator.
21* Run `make emu` to build the C++ simulator `./build/emu` with Verilator.
22* Refer to `./build/emu --help` for run-time arguments of the simulator.
23* Refer to `Makefile` and `verilator.mk` for more information.
24
25Example:
26```bash
27make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10
28./build/emu -b 0 -e 0 -i $AM_HOME/apps/coremark/build/coremark-riscv64-noop.bin
29```
30
31## Generate Verilog
32* Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`.
33* Refer to `Makefile` for more information.
34