1# XiangShan 2 3XiangShan (香山) is an open-source high-performance RISC-V processor project. 4 5中文说明[在此](readme.zh-cn.md)。 6 7Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences. 8 9## Docs and slides 10We gave 20+ presentations on RISC-V World Conference China 2021. XiangShan tutorial was held at the same place. Our slides for RVWC2021 have been updated on [our doc repo](https://github.com/OpenXiangShan/XiangShan-doc) (in Chinese). 11 12我们在2021年RISC-V中国峰会的报告已经更新到[这里](https://github.com/OpenXiangShan/XiangShan-doc)。未来的文档和相关信息也将更新到相同的仓库。 13 14## Mail list 15You can contact us through [our mail list](mailto:[email protected]). All mails from this list will be archived to [here](https://www.mail-archive.com/[email protected]/). 16 17## Architecture 18 19The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch. 20 21The micro-architecture overview is shown below. 22 23 24 25 26 27## Sub-directories Overview 28 29Some of the key directories are shown below. 30 31``` 32. 33├── fpga # supported FPGA boards and files to build a Vivado project 34├── read-to-run # pre-built simulation images 35├── scripts # scripts for agile development 36└── src 37 ├── test # test files (including diff-test, module-test, etc.) 38 └── main/scala # design files 39 ├── bus/tilelink # tilelink utils 40 ├── device # virtual device for simulation 41 ├── difftest # diff-test chisel interface 42 ├── system # SoC wrapper 43 ├── top # top module 44 ├── utils # utilization code 45 ├── xiangshan # main design code 46 └── xstransforms # some useful firrtl transforms 47``` 48 49 50 51## Generate Verilog 52 53* Run `make verilog` to generate verilog code. The output file is `build/XSTop.v`. 54* Refer to `Makefile` for more information. 55 56 57 58## Run Programs by Simulation 59 60### Prepare environment 61 62* Set environment variable `NEMU_HOME` to the **absolute path** of the [NEMU project](https://github.com/OpenXiangShan/NEMU). 63* Set environment variable `NOOP_HOME` to the **absolute path** of the XiangShan project. 64* Set environment variable `AM_HOME` to the **absolute path** of the [AM project](https://github.com/OpenXiangShan/nexus-am). 65* Install `mill`. Refer to [the Manual section in this guide](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation). 66* Clone this project and run `make init` to initialize submodules. 67 68### Run with simulator 69 70* Install [Verilator](https://verilator.org/guide/latest/), the open-source Verilog simulator. 71* Run `make emu` to build the C++ simulator `./build/emu` with Verilator. 72* Refer to `./build/emu --help` for run-time arguments of the simulator. 73* Refer to `Makefile` and `verilator.mk` for more information. 74 75Example: 76 77```bash 78make emu CONFIG=MinimalConfig SIM_ARGS=--disable-log EMU_THREADS=2 -j10 79./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so 80``` 81 82## Acknowledgement 83 84In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below. 85 86| Sub-module | Source | Detail | 87| ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ | 88| L2 Cache/LLC | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | We enhance the function and the timing of the original module, finally turning it into a Cache generator that can be configured as L2/LLC. | 89| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | 90| FPU | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | We use Berkeley-hardfloat as our FPU and implement an SRT-4 div/sqrt unit for it. Additionally, we split the FMA pipeline to optimize the timing. | 91 92We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE). 93 94
