xref: /XiangShan/Makefile (revision fda2de2d149f9d06289993edc3d42476f7326197) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17TOP = XSTop
18FPGATOP = top.TopMain
19BUILD_DIR = ./build
20TOP_V = $(BUILD_DIR)/$(TOP).v
21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
22TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
23MEM_GEN = ./scripts/vlsi_mem_gen
24
25SIMTOP  = top.SimTop
26IMAGE  ?= temp
27CONFIG ?= DefaultConfig
28NUM_CORES ?= 1
29MFC ?= 0
30
31FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
32SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
33
34# select firrtl compiler
35ifeq ($(MFC),1)
36override FC_ARGS = --mfc
37override FPGA_MEM_ARGS = --infer-rw
38override SIM_MEM_ARGS = --infer-rw
39endif
40
41
42# co-simulation with DRAMsim3
43ifeq ($(WITH_DRAMSIM3),1)
44ifndef DRAMSIM3_HOME
45$(error DRAMSIM3_HOME is not set)
46endif
47override SIM_ARGS += --with-dramsim3
48endif
49
50# top-down
51ifeq ($(ENABLE_TOPDOWN),1)
52override SIM_ARGS += --enable-topdown
53endif
54
55# emu for the release version
56RELEASE_ARGS = --disable-all --remove-assert --fpga-platform
57DEBUG_ARGS   = --enable-difftest
58ifeq ($(RELEASE),1)
59override SIM_ARGS += $(RELEASE_ARGS)
60else
61override SIM_ARGS += $(DEBUG_ARGS)
62endif
63
64TIMELOG = $(BUILD_DIR)/time.log
65TIME_CMD = time -a -o $(TIMELOG)
66
67SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
68
69# add comments to 'firrtl_black_box_resource_files'
70AWK_CMD = gawk -i inplace 'BEGIN{f=0} /FILE "firrtl_black_box_resource_files.f"/{f=1} !f{print $$0} f{print "//", $$0}'
71
72
73.DEFAULT_GOAL = verilog
74
75help:
76	mill -i XiangShan.runMain $(FPGATOP) --help
77
78$(TOP_V): $(SCALA_FILE)
79	mkdir -p $(@D)
80	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)  \
81		--config $(CONFIG)                                        \
82		$(FPGA_MEM_ARGS)                                          \
83		--num-cores $(NUM_CORES)                                  \
84		$(RELEASE_ARGS) $(FC_ARGS)
85	$(SED_CMD) $@
86ifeq ($(MFC),1)
87	$(AWK_CMD) $@
88endif
89	@git log -n 1 >> .__head__
90	@git diff >> .__diff__
91	@sed -i 's/^/\/\// ' .__head__
92	@sed -i 's/^/\/\//' .__diff__
93	@cat .__head__ .__diff__ $@ > .__out__
94	@mv .__out__ $@
95	@rm .__head__ .__diff__
96
97verilog: $(TOP_V)
98
99SIM_TOP   = SimTop
100SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
101$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
102	mkdir -p $(@D)
103	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
104	@date -R | tee -a $(TIMELOG)
105	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)  \
106		--config $(CONFIG)                                            \
107		$(SIM_MEM_ARGS)                                               \
108		--num-cores $(NUM_CORES)                                      \
109		$(SIM_ARGS) $(FC_ARGS)
110	$(SED_CMD) $@
111ifeq ($(MFC),1)
112	$(AWK_CMD) $@
113endif
114	@git log -n 1 >> .__head__
115	@git diff >> .__diff__
116	@sed -i 's/^/\/\// ' .__head__
117	@sed -i 's/^/\/\//' .__diff__
118	@cat .__head__ .__diff__ $@ > .__out__
119	@mv .__out__ $@
120	@rm .__head__ .__diff__
121	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
122
123sim-verilog: $(SIM_TOP_V)
124
125clean:
126	$(MAKE) -C ./difftest clean
127	rm -rf ./build
128
129init:
130	git submodule update --init
131	cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
132
133bump:
134	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
135
136bsp:
137	mill -i mill.bsp.BSP/install
138
139idea:
140	mill -i mill.scalalib.GenIdea/idea
141
142# verilator simulation
143emu:
144	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
145
146emu-run:
147	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
148
149# vcs simulation
150simv:
151	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
152
153include Makefile.test
154
155.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
156