1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17BUILD_DIR = ./build 18RTL_DIR = $(BUILD_DIR)/rtl 19 20TOP = XSTop 21SIM_TOP = SimTop 22 23FPGATOP = top.TopMain 24SIMTOP = top.SimTop 25 26TOP_V = $(RTL_DIR)/$(TOP).v 27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v 28 29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 30TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 31 32MEM_GEN = ./scripts/vlsi_mem_gen 33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 34SPLIT_VERILOG = ./scripts/split_verilog.sh 35 36IMAGE ?= temp 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39MFC ?= 0 40 41 42ifeq ($(MAKECMDGOALS),) 43GOALS = verilog 44else 45GOALS = $(MAKECMDGOALS) 46endif 47 48# common chisel args 49ifeq ($(MFC),1) 50CHISEL_VERSION = chisel 51FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 52SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 53MFC_ARGS = --dump-fir --target verilog \ 54 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 55RELEASE_ARGS += $(MFC_ARGS) 56DEBUG_ARGS += $(MFC_ARGS) 57PLDM_ARGS += $(MFC_ARGS) 58else 59CHISEL_VERSION = chisel3 60FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 61SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 62endif 63 64ifneq ($(XSTOP_PREFIX),) 65RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 66DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68endif 69 70# co-simulation with DRAMsim3 71ifeq ($(WITH_DRAMSIM3),1) 72ifndef DRAMSIM3_HOME 73$(error DRAMSIM3_HOME is not set) 74endif 75override SIM_ARGS += --with-dramsim3 76endif 77 78# run emu with chisel-db 79ifeq ($(WITH_CHISELDB),1) 80override SIM_ARGS += --with-chiseldb 81endif 82 83# run emu with chisel-db 84ifeq ($(WITH_ROLLINGDB),1) 85override SIM_ARGS += --with-rollingdb 86endif 87 88# dynamic switch CONSTANTIN 89ifeq ($(WITH_CONSTANTIN),0) 90$(info disable WITH_CONSTANTIN) 91else 92override SIM_ARGS += --with-constantin 93endif 94 95# emu for the release version 96RELEASE_ARGS += --fpga-platform --disable-all --remove-assert 97DEBUG_ARGS += --enable-difftest 98PLDM_ARGS += --fpga-platform --enable-difftest 99ifeq ($(GOALS),verilog) 100RELEASE_ARGS += --disable-always-basic-diff 101endif 102ifeq ($(RELEASE),1) 103override SIM_ARGS += $(RELEASE_ARGS) 104else ifeq ($(PLDM),1) 105override SIM_ARGS += $(PLDM_ARGS) 106else 107override SIM_ARGS += $(DEBUG_ARGS) 108endif 109 110TIMELOG = $(BUILD_DIR)/time.log 111TIME_CMD = time -a -o $(TIMELOG) 112 113SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 114 115ifeq ($(PLDM),1) 116SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 117SED_ENDIF = `endif // not def SYNTHESIS 118endif 119 120.DEFAULT_GOAL = verilog 121 122help: 123 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 124 125$(TOP_V): $(SCALA_FILE) 126 mkdir -p $(@D) 127 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 128 -td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 129 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 130ifeq ($(MFC),1) 131 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v 132 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)" 133endif 134 $(SED_CMD) $@ 135 @git log -n 1 >> .__head__ 136 @git diff >> .__diff__ 137 @sed -i 's/^/\/\// ' .__head__ 138 @sed -i 's/^/\/\//' .__diff__ 139 @cat .__head__ .__diff__ $@ > .__out__ 140 @mv .__out__ $@ 141 @rm .__head__ .__diff__ 142 143verilog: $(TOP_V) 144 145$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 146 mkdir -p $(@D) 147 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 148 @date -R | tee -a $(TIMELOG) 149 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 150 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 151 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 152ifeq ($(MFC),1) 153 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v 154 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 155endif 156 $(SED_CMD) $@ 157 @git log -n 1 >> .__head__ 158 @git diff >> .__diff__ 159 @sed -i 's/^/\/\// ' .__head__ 160 @sed -i 's/^/\/\//' .__diff__ 161 @cat .__head__ .__diff__ $@ > .__out__ 162 @mv .__out__ $@ 163 @rm .__head__ .__diff__ 164ifeq ($(PLDM),1) 165 sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V) 166 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(SIM_TOP_V) 167else 168 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 169endif 170ifeq ($(MFC),1) 171 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V) 172endif 173 174sim-verilog: $(SIM_TOP_V) 175 176clean: 177 $(MAKE) -C ./difftest clean 178 rm -rf $(BUILD_DIR) 179 180init: 181 git submodule update --init 182 cd rocket-chip && git submodule update --init cde hardfloat 183 184bump: 185 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 186 187bsp: 188 mill -i mill.bsp.BSP/install 189 190idea: 191 mill -i mill.scalalib.GenIdea/idea 192 193# verilator simulation 194emu: sim-verilog 195 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 196 197emu-run: emu 198 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 199 200# vcs simulation 201simv: sim-verilog 202 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 203 204# palladium simulation 205pldm-build: sim-verilog 206 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 207 208pldm-run: 209 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 210 211pldm-debug: 212 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 213 214include Makefile.test 215 216.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 217