1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17TOP = XSTop 18FPGATOP = top.TopMain 19BUILD_DIR = ./build 20TOP_V = $(BUILD_DIR)/$(TOP).v 21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 22TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 23MEM_GEN = ./scripts/vlsi_mem_gen 24MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 25 26SIMTOP = top.SimTop 27IMAGE ?= temp 28CONFIG ?= DefaultConfig 29NUM_CORES ?= 1 30MFC ?= 0 31 32FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 33SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 34 35# select firrtl compiler 36ifeq ($(MFC),1) 37override FC_ARGS = --mfc 38override FPGA_MEM_ARGS = --infer-rw --firtool-opt -split-verilog --firtool-opt -o --firtool-opt build --firtool-opt -repl-seq-mem --firtool-opt -repl-seq-mem-circuit=$(FPGATOP) --firtool-opt -repl-seq-mem-file=XSTop.v.conf 39override SIM_MEM_ARGS = --infer-rw --firtool-opt -split-verilog --firtool-opt -o --firtool-opt build --firtool-opt -repl-seq-mem --firtool-opt -repl-seq-mem-circuit=$(SIMTOP) --firtool-opt -repl-seq-mem-file=SimTop.v.conf 40endif 41 42 43# co-simulation with DRAMsim3 44ifeq ($(WITH_DRAMSIM3),1) 45ifndef DRAMSIM3_HOME 46$(error DRAMSIM3_HOME is not set) 47endif 48override SIM_ARGS += --with-dramsim3 49endif 50 51# run emu with chisel-db 52ifeq ($(WITH_CHISELDB),1) 53override SIM_ARGS += --with-chiseldb 54endif 55 56# run emu with chisel-db 57ifeq ($(WITH_ROLLINGDB),1) 58override SIM_ARGS += --with-rollingdb 59endif 60 61# dynamic switch CONSTANTIN 62ifeq ($(WITH_CONSTANTIN),0) 63$(info disable WITH_CONSTANTIN) 64else 65override SIM_ARGS += --with-constantin 66endif 67 68# emu for the release version 69RELEASE_ARGS = --disable-all --remove-assert --fpga-platform 70DEBUG_ARGS = --enable-difftest 71ifeq ($(RELEASE),1) 72override SIM_ARGS += $(RELEASE_ARGS) 73else 74override SIM_ARGS += $(DEBUG_ARGS) 75endif 76 77TIMELOG = $(BUILD_DIR)/time.log 78TIME_CMD = time -a -o $(TIMELOG) 79 80SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 81 82.DEFAULT_GOAL = verilog 83 84help: 85 mill -i XiangShan.runMain $(FPGATOP) --help 86 87$(TOP_V): $(SCALA_FILE) 88 mkdir -p $(@D) 89 $(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \ 90 --config $(CONFIG) \ 91 $(FPGA_MEM_ARGS) \ 92 --num-cores $(NUM_CORES) \ 93 $(RELEASE_ARGS) $(FC_ARGS) 94ifeq ($(MFC),1) 95 for file in $(BUILD_DIR)/*.sv; do $(SED_CMD) "$${file}"; mv "$${file}" "$${file%.sv}.v"; done 96 mv $(BUILD_DIR)/$(BUILD_DIR)/* $(BUILD_DIR) 97 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)" 98endif 99 $(SED_CMD) $@ 100 @git log -n 1 >> .__head__ 101 @git diff >> .__diff__ 102 @sed -i 's/^/\/\// ' .__head__ 103 @sed -i 's/^/\/\//' .__diff__ 104 @cat .__head__ .__diff__ $@ > .__out__ 105 @mv .__out__ $@ 106 @rm .__head__ .__diff__ 107 108verilog: $(TOP_V) 109 110SIM_TOP = SimTop 111SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v 112$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 113 mkdir -p $(@D) 114 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 115 @date -R | tee -a $(TIMELOG) 116 $(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \ 117 --config $(CONFIG) \ 118 $(SIM_MEM_ARGS) \ 119 --num-cores $(NUM_CORES) \ 120 $(SIM_ARGS) $(FC_ARGS) 121ifeq ($(MFC),1) 122 for file in $(BUILD_DIR)/*.sv; do $(SED_CMD) "$${file}"; mv "$${file}" "$${file%.sv}.v"; done 123 mv $(BUILD_DIR)/$(BUILD_DIR)/* $(BUILD_DIR) 124 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)" 125endif 126 $(SED_CMD) $@ 127 @git log -n 1 >> .__head__ 128 @git diff >> .__diff__ 129 @sed -i 's/^/\/\// ' .__head__ 130 @sed -i 's/^/\/\//' .__diff__ 131 @cat .__head__ .__diff__ $@ > .__out__ 132 @mv .__out__ $@ 133 @rm .__head__ .__diff__ 134 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 135 136sim-verilog: $(SIM_TOP_V) 137 138clean: 139 $(MAKE) -C ./difftest clean 140 rm -rf ./build 141 142init: 143 git submodule update --init 144 cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat 145 146bump: 147 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 148 149bsp: 150 mill -i mill.bsp.BSP/install 151 152idea: 153 mill -i mill.scalalib.GenIdea/idea 154 155# verilator simulation 156emu: sim-verilog 157 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 158 159emu-run: emu 160 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 161 162# vcs simulation 163simv: 164 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 165 166include Makefile.test 167 168.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 169