1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17BUILD_DIR = ./build 18 19TOP = XSTop 20SIM_TOP = SimTop 21 22FPGATOP = top.TopMain 23SIMTOP = top.SimTop 24 25TOP_V = $(BUILD_DIR)/$(TOP).v 26SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v 27 28SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 29TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 30 31MEM_GEN = ./scripts/vlsi_mem_gen 32MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 33SPLIT_VERILOG = ./scripts/split_verilog.sh 34 35IMAGE ?= temp 36CONFIG ?= DefaultConfig 37NUM_CORES ?= 1 38MFC ?= 0 39 40# firtool check and download 41FIRTOOL_VERSION = 1.61.0 42FIRTOOL_URL = https://github.com/llvm/circt/releases/download/firtool-$(FIRTOOL_VERSION)/firrtl-bin-linux-x64.tar.gz 43FIRTOOL_PATH = $(shell which firtool 2>/dev/null) 44CACHE_FIRTOOL_PATH = $(HOME)/.cache/xiangshan/firtool-$(FIRTOOL_VERSION)/bin/firtool 45ifeq ($(MFC),1) 46ifeq ($(FIRTOOL_PATH),) 47ifeq ($(wildcard $(CACHE_FIRTOOL_PATH)),) 48$(info [INFO] Firtool not found in your PATH.) 49$(info [INFO] Downloading from $(FIRTOOL_URL)) 50$(shell mkdir -p $(HOME)/.cache/xiangshan && curl -L $(FIRTOOL_URL) | tar -xzC $(HOME)/.cache/xiangshan) 51endif 52FIRTOOL_ARGS = --firtool-binary-path $(CACHE_FIRTOOL_PATH) 53endif 54endif 55 56# common chisel args 57ifeq ($(MFC),1) 58CHISEL_VERSION = chisel 59FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 60SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 61MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \ 62 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing" 63RELEASE_ARGS += $(MFC_ARGS) 64DEBUG_ARGS += $(MFC_ARGS) 65PLDM_ARGS += $(MFC_ARGS) 66else 67CHISEL_VERSION = chisel3 68FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 69SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 70endif 71 72# co-simulation with DRAMsim3 73ifeq ($(WITH_DRAMSIM3),1) 74ifndef DRAMSIM3_HOME 75$(error DRAMSIM3_HOME is not set) 76endif 77override SIM_ARGS += --with-dramsim3 78endif 79 80# run emu with chisel-db 81ifeq ($(WITH_CHISELDB),1) 82override SIM_ARGS += --with-chiseldb 83endif 84 85# run emu with chisel-db 86ifeq ($(WITH_ROLLINGDB),1) 87override SIM_ARGS += --with-rollingdb 88endif 89 90# dynamic switch CONSTANTIN 91ifeq ($(WITH_CONSTANTIN),0) 92$(info disable WITH_CONSTANTIN) 93else 94override SIM_ARGS += --with-constantin 95endif 96 97# emu for the release version 98RELEASE_ARGS += --disable-all --remove-assert --fpga-platform 99DEBUG_ARGS += --enable-difftest 100PLDM_ARGS += --disable-all --fpga-platform 101ifeq ($(RELEASE),1) 102override SIM_ARGS += $(RELEASE_ARGS) 103else ifeq ($(PLDM),1) 104override SIM_ARGS += $(PLDM_ARGS) 105else 106override SIM_ARGS += $(DEBUG_ARGS) 107endif 108 109TIMELOG = $(BUILD_DIR)/time.log 110TIME_CMD = time -a -o $(TIMELOG) 111 112SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 113 114.DEFAULT_GOAL = verilog 115 116help: 117 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 118 119$(TOP_V): $(SCALA_FILE) 120 mkdir -p $(@D) 121 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 122 -td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 123 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 124ifeq ($(MFC),1) 125 $(SPLIT_VERILOG) $(BUILD_DIR) $(TOP).v 126 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)" 127endif 128 $(SED_CMD) $@ 129 @git log -n 1 >> .__head__ 130 @git diff >> .__diff__ 131 @sed -i 's/^/\/\// ' .__head__ 132 @sed -i 's/^/\/\//' .__diff__ 133 @cat .__head__ .__diff__ $@ > .__out__ 134 @mv .__out__ $@ 135 @rm .__head__ .__diff__ 136 137verilog: $(TOP_V) 138 139$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 140 mkdir -p $(@D) 141 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 142 @date -R | tee -a $(TIMELOG) 143 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 144 -td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 145 --num-cores $(NUM_CORES) $(SIM_ARGS) 146ifeq ($(MFC),1) 147 $(SPLIT_VERILOG) $(BUILD_DIR) $(SIM_TOP).v 148 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)" 149endif 150 $(SED_CMD) $@ 151 @git log -n 1 >> .__head__ 152 @git diff >> .__diff__ 153 @sed -i 's/^/\/\// ' .__head__ 154 @sed -i 's/^/\/\//' .__diff__ 155 @cat .__head__ .__diff__ $@ > .__out__ 156 @mv .__out__ $@ 157 @rm .__head__ .__diff__ 158ifeq ($(PLDM),1) 159 sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V) 160 sed -i -e 's|`ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala:141:11|`ifdef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala:141:11|g' $(SIM_TOP_V) 161else 162 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 163endif 164ifeq ($(MFC),1) 165 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V) 166endif 167 168sim-verilog: $(SIM_TOP_V) 169 170clean: 171 $(MAKE) -C ./difftest clean 172 rm -rf $(BUILD_DIR) 173 174init: 175 git submodule update --init 176 cd rocket-chip && git submodule update --init cde hardfloat 177 178bump: 179 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 180 181bsp: 182 mill -i mill.bsp.BSP/install 183 184idea: 185 mill -i mill.scalalib.GenIdea/idea 186 187# verilator simulation 188emu: sim-verilog 189 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 190 191emu-run: emu 192 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 193 194# vcs simulation 195simv: 196 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 197 198include Makefile.test 199 200.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 201