1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# 4# XiangShan is licensed under Mulan PSL v2. 5# You can use this software according to the terms and conditions of the Mulan PSL v2. 6# You may obtain a copy of Mulan PSL v2 at: 7# http://license.coscl.org.cn/MulanPSL2 8# 9# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12# 13# See the Mulan PSL v2 for more details. 14#*************************************************************************************** 15 16TOP = XSTop 17FPGATOP = top.TopMain 18BUILD_DIR = ./build 19TOP_V = $(BUILD_DIR)/$(TOP).v 20SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 21TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 22MEM_GEN = ./scripts/vlsi_mem_gen 23 24SIMTOP = top.SimTop 25IMAGE ?= temp 26CONFIG ?= DefaultConfig 27 28# co-simulation with DRAMsim3 29ifeq ($(WITH_DRAMSIM3),1) 30ifndef DRAMSIM3_HOME 31$(error DRAMSIM3_HOME is not set) 32endif 33override SIM_ARGS += --with-dramsim3 34endif 35 36TIMELOG = $(BUILD_DIR)/time.log 37TIME_CMD = time -a -o $(TIMELOG) 38 39# remote machine with more cores to speedup c++ build 40REMOTE ?= localhost 41 42.DEFAULT_GOAL = verilog 43 44help: 45 mill XiangShan.test.runMain $(SIMTOP) --help 46 47$(TOP_V): $(SCALA_FILE) 48 mkdir -p $(@D) 49 mill XiangShan.test.runMain $(FPGATOP) -td $(@D) --config $(CONFIG) --full-stacktrace --output-file $(@F) --disable-all --remove-assert --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf $(SIM_ARGS) 50 $(MEM_GEN) $(@D)/$(@F).conf --tsmc28 --output_file $(@D)/tsmc28_sram.v > $(@D)/tsmc28_sram.v.conf 51 $(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/sim_sram.v 52 # sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@ 53 @git log -n 1 >> .__head__ 54 @git diff >> .__diff__ 55 @sed -i 's/^/\/\// ' .__head__ 56 @sed -i 's/^/\/\//' .__diff__ 57 @cat .__head__ .__diff__ $@ > .__out__ 58 @mv .__out__ $@ 59 @rm .__head__ .__diff__ 60 61deploy: build/top.zip 62 63 64build/top.zip: $(TOP_V) 65 @zip -r $@ $< $<.conf build/*.anno.json 66 67.PHONY: deploy build/top.zip 68 69verilog: $(TOP_V) 70 71SIM_TOP = SimTop 72SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v 73$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 74 mkdir -p $(@D) 75 @echo "\n[mill] Generating Verilog files..." > $(TIMELOG) 76 @date -R | tee -a $(TIMELOG) 77 $(TIME_CMD) mill XiangShan.test.runMain $(SIMTOP) -td $(@D) --config $(CONFIG) --full-stacktrace --output-file $(@F) --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf $(SIM_ARGS) 78 $(MEM_GEN) $(@D)/$(@F).conf --output_file $(@D)/$(@F).sram.v 79 @git log -n 1 >> .__head__ 80 @git diff >> .__diff__ 81 @sed -i 's/^/\/\// ' .__head__ 82 @sed -i 's/^/\/\//' .__diff__ 83 @cat .__head__ .__diff__ $@ $(@D)/$(@F).sram.v > .__out__ 84 @mv .__out__ $@ 85 @rm .__head__ .__diff__ 86 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 87 88sim-verilog: $(SIM_TOP_V) 89 90SIM_CSRC_DIR = $(abspath ./src/test/csrc/common) 91SIM_CXXFILES = $(shell find $(SIM_CSRC_DIR) -name "*.cpp") 92 93DIFFTEST_CSRC_DIR = $(abspath ./src/test/csrc/difftest) 94DIFFTEST_CXXFILES = $(shell find $(DIFFTEST_CSRC_DIR) -name "*.cpp") 95 96SIM_VSRC = $(shell find ./src/test/vsrc/common -name "*.v" -or -name "*.sv") 97 98include verilator.mk 99include vcs.mk 100 101ifndef NEMU_HOME 102$(error NEMU_HOME is not set) 103endif 104REF_SO := $(NEMU_HOME)/build/riscv64-nemu-interpreter-so 105$(REF_SO): 106 $(MAKE) -C $(NEMU_HOME) ISA=riscv64 SHARE=1 107 108SEED ?= $(shell shuf -i 1-10000 -n 1) 109 110VME_SOURCE ?= $(shell pwd)/build/$(TOP).v 111VME_MODULES ?= 112 113#-----------------------timing scripts------------------------- 114# run "make vme/tap help=1" to get help info 115 116# extract verilog module from TopMain.v 117# usage: make vme VME_MODULES=Roq 118TIMING_SCRIPT_PATH = ./timingScripts 119vme: $(TOP_V) 120 make -C $(TIMING_SCRIPT_PATH) vme 121 122# get and sort timing analysis with total delay(start+end) and max delay(start or end) 123# and print it out 124tap: 125 make -C $(TIMING_SCRIPT_PATH) tap 126 127# usage: make phy_evaluate VME_MODULE=Roq REMOTE=100 128phy_evaluate: vme 129 scp -r ./build/extracted/* $(REMOTE):~/phy_evaluation/remote_run/rtl 130 ssh -tt $(REMOTE) 'cd ~/phy_evaluation/remote_run && $(MAKE) evaluate DESIGN_NAME=$(VME_MODULE)' 131 scp -r $(REMOTE):~/phy_evaluation/remote_run/rpts ./build 132 133# usage: make phy_evaluate_atc VME_MODULE=Roq REMOTE=100 134phy_evaluate_atc: vme 135 scp -r ./build/extracted/* $(REMOTE):~/phy_evaluation/remote_run/rtl 136 ssh -tt $(REMOTE) 'cd ~/phy_evaluation/remote_run && $(MAKE) evaluate_atc DESIGN_NAME=$(VME_MODULE)' 137 scp -r $(REMOTE):~/phy_evaluation/remote_run/rpts ./build 138 139cache: 140 $(MAKE) emu IMAGE=Makefile 141 142release-lock: 143 ssh -tt $(REMOTE) 'rm -f $(LOCK)' 144 145clean: vcs-clean 146 rm -rf ./build 147 148init: 149 git submodule update --init 150 151bump: 152 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 153 154bsp: 155 mill -i mill.bsp.BSP/install 156 157.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 158 159