1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39MFC ?= 1 40 41ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 42$(error At most one target can be specified) 43endif 44 45ifeq ($(MAKECMDGOALS),) 46GOALS = verilog 47else 48GOALS = $(MAKECMDGOALS) 49endif 50 51# common chisel args 52ifeq ($(MFC),1) 53CHISEL_VERSION = chisel 54FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 55SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 56MFC_ARGS = --dump-fir --target systemverilog --split-verilog \ 57 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 58RELEASE_ARGS += $(MFC_ARGS) 59DEBUG_ARGS += $(MFC_ARGS) 60PLDM_ARGS += $(MFC_ARGS) 61else 62CHISEL_VERSION = chisel3 63FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 64SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 65endif 66 67ifneq ($(XSTOP_PREFIX),) 68RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 69DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 70PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 71endif 72 73ifeq ($(IMSIC_USE_TL),1) 74RELEASE_ARGS += --imsic-use-tl 75DEBUG_ARGS += --imsic-use-tl 76PLDM_ARGS += --imsic-use-tl 77endif 78 79# co-simulation with DRAMsim3 80ifeq ($(WITH_DRAMSIM3),1) 81ifndef DRAMSIM3_HOME 82$(error DRAMSIM3_HOME is not set) 83endif 84override SIM_ARGS += --with-dramsim3 85endif 86 87# run emu with chisel-db 88ifeq ($(WITH_CHISELDB),1) 89override SIM_ARGS += --with-chiseldb 90endif 91 92# run emu with chisel-db 93ifeq ($(WITH_ROLLINGDB),1) 94override SIM_ARGS += --with-rollingdb 95endif 96 97# enable ResetGen 98ifeq ($(WITH_RESETGEN),1) 99override SIM_ARGS += --reset-gen 100endif 101 102# run with disable all perf 103ifeq ($(DISABLE_PERF),1) 104override SIM_ARGS += --disable-perf 105endif 106 107# run with disable all db 108ifeq ($(DISABLE_ALWAYSDB),1) 109override SIM_ARGS += --disable-alwaysdb 110endif 111 112# dynamic switch CONSTANTIN 113ifeq ($(WITH_CONSTANTIN),1) 114override SIM_ARGS += --with-constantin 115endif 116 117# emu for the release version 118RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen 119DEBUG_ARGS += --enable-difftest 120PLDM_ARGS += --fpga-platform --enable-difftest 121ifeq ($(GOALS),verilog) 122RELEASE_ARGS += --disable-always-basic-diff 123endif 124ifeq ($(RELEASE),1) 125override SIM_ARGS += $(RELEASE_ARGS) 126else ifeq ($(PLDM),1) 127override SIM_ARGS += $(PLDM_ARGS) 128else 129override SIM_ARGS += $(DEBUG_ARGS) 130endif 131 132TIMELOG = $(BUILD_DIR)/time.log 133TIME_CMD = time -avp -o $(TIMELOG) 134 135ifeq ($(PLDM),1) 136SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 137SED_ENDIF = `endif // not def SYNTHESIS 138endif 139 140.DEFAULT_GOAL = verilog 141 142help: 143 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 144 145$(TOP_V): $(SCALA_FILE) 146 mkdir -p $(@D) 147 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 148 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 149 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 150ifeq ($(MFC),1) 151 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 152endif 153 @git log -n 1 >> .__head__ 154 @git diff >> .__diff__ 155 @sed -i 's/^/\/\// ' .__head__ 156 @sed -i 's/^/\/\//' .__diff__ 157 @cat .__head__ .__diff__ $@ > .__out__ 158 @mv .__out__ $@ 159 @rm .__head__ .__diff__ 160 161verilog: $(TOP_V) 162 163$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 164 mkdir -p $(@D) 165 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 166 @date -R | tee -a $(TIMELOG) 167 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 168 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 169 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 170ifeq ($(MFC),1) 171 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 172endif 173 @git log -n 1 >> .__head__ 174 @git diff >> .__diff__ 175 @sed -i 's/^/\/\// ' .__head__ 176 @sed -i 's/^/\/\//' .__diff__ 177 @cat .__head__ .__diff__ $@ > .__out__ 178 @mv .__out__ $@ 179 @rm .__head__ .__diff__ 180ifeq ($(PLDM),1) 181 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 182 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 183else 184ifeq ($(ENABLE_XPROP),1) 185 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 186else 187 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 188endif 189endif 190ifeq ($(MFC),1) 191 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 192endif 193 194sim-verilog: $(SIM_TOP_V) 195 196clean: 197 $(MAKE) -C ./difftest clean 198 rm -rf $(BUILD_DIR) 199 200init: 201 git submodule update --init 202 cd rocket-chip && git submodule update --init cde hardfloat 203 204bump: 205 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 206 207bsp: 208 mill -i mill.bsp.BSP/install 209 210idea: 211 mill -i mill.scalalib.GenIdea/idea 212 213# verilator simulation 214emu: sim-verilog 215 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 216 217emu-run: emu 218 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 219 220# vcs simulation 221simv: sim-verilog 222 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 223 224simv-run: 225 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 226 227# palladium simulation 228pldm-build: sim-verilog 229 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 230 231pldm-run: 232 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 233 234pldm-debug: 235 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 236 237include Makefile.test 238 239include src/main/scala/device/standalone/standalone_device.mk 240 241.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 242