1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39 40ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 41$(error At most one target can be specified) 42endif 43 44ifeq ($(MAKECMDGOALS),) 45GOALS = verilog 46else 47GOALS = $(MAKECMDGOALS) 48endif 49 50# common chisel args 51FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 52SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 53MFC_ARGS = --dump-fir --target systemverilog --split-verilog \ 54 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 55RELEASE_ARGS += $(MFC_ARGS) 56DEBUG_ARGS += $(MFC_ARGS) 57PLDM_ARGS += $(MFC_ARGS) 58 59ifneq ($(XSTOP_PREFIX),) 60RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 61DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 62PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 63endif 64 65ifeq ($(IMSIC_USE_TL),1) 66RELEASE_ARGS += --imsic-use-tl 67DEBUG_ARGS += --imsic-use-tl 68PLDM_ARGS += --imsic-use-tl 69endif 70 71# co-simulation with DRAMsim3 72ifeq ($(WITH_DRAMSIM3),1) 73ifndef DRAMSIM3_HOME 74$(error DRAMSIM3_HOME is not set) 75endif 76override SIM_ARGS += --with-dramsim3 77endif 78 79# run emu with chisel-db 80ifeq ($(WITH_CHISELDB),1) 81override SIM_ARGS += --with-chiseldb 82endif 83 84# run emu with chisel-db 85ifeq ($(WITH_ROLLINGDB),1) 86override SIM_ARGS += --with-rollingdb 87endif 88 89# enable ResetGen 90ifeq ($(WITH_RESETGEN),1) 91override SIM_ARGS += --reset-gen 92endif 93 94# run with disable all perf 95ifeq ($(DISABLE_PERF),1) 96override SIM_ARGS += --disable-perf 97endif 98 99# run with disable all db 100ifeq ($(DISABLE_ALWAYSDB),1) 101override SIM_ARGS += --disable-alwaysdb 102endif 103 104# dynamic switch CONSTANTIN 105ifeq ($(WITH_CONSTANTIN),1) 106override SIM_ARGS += --with-constantin 107endif 108 109# emu for the release version 110RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen 111DEBUG_ARGS += --enable-difftest 112PLDM_ARGS += --fpga-platform --enable-difftest 113ifeq ($(GOALS),verilog) 114RELEASE_ARGS += --disable-always-basic-diff 115endif 116ifeq ($(RELEASE),1) 117override SIM_ARGS += $(RELEASE_ARGS) 118else ifeq ($(PLDM),1) 119override SIM_ARGS += $(PLDM_ARGS) 120else 121override SIM_ARGS += $(DEBUG_ARGS) 122endif 123 124TIMELOG = $(BUILD_DIR)/time.log 125TIME_CMD = time -avp -o $(TIMELOG) 126 127ifeq ($(PLDM),1) 128SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 129SED_ENDIF = `endif // not def SYNTHESIS 130endif 131 132.DEFAULT_GOAL = verilog 133 134help: 135 mill -i xiangshan.runMain $(FPGATOP) --help 136 137$(TOP_V): $(SCALA_FILE) 138 mkdir -p $(@D) 139 $(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP) \ 140 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 141 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 142 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 143 @git log -n 1 >> .__head__ 144 @git diff >> .__diff__ 145 @sed -i 's/^/\/\// ' .__head__ 146 @sed -i 's/^/\/\//' .__diff__ 147 @cat .__head__ .__diff__ $@ > .__out__ 148 @mv .__out__ $@ 149 @rm .__head__ .__diff__ 150 151verilog: $(TOP_V) 152 153$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 154 mkdir -p $(@D) 155 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 156 @date -R | tee -a $(TIMELOG) 157 $(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP) \ 158 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 159 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 160 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 161 @git log -n 1 >> .__head__ 162 @git diff >> .__diff__ 163 @sed -i 's/^/\/\// ' .__head__ 164 @sed -i 's/^/\/\//' .__diff__ 165 @cat .__head__ .__diff__ $@ > .__out__ 166 @mv .__out__ $@ 167 @rm .__head__ .__diff__ 168ifeq ($(PLDM),1) 169 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 170 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 171else 172ifeq ($(ENABLE_XPROP),1) 173 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 174else 175 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 176endif 177endif 178 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 179 180sim-verilog: $(SIM_TOP_V) 181 182clean: 183 $(MAKE) -C ./difftest clean 184 rm -rf $(BUILD_DIR) 185 186init: 187 git submodule update --init 188 cd rocket-chip && git submodule update --init cde hardfloat 189 190bump: 191 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 192 193bsp: 194 mill -i mill.bsp.BSP/install 195 196idea: 197 mill -i mill.idea.GenIdea/idea 198 199# verilator simulation 200emu: sim-verilog 201 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 202 203emu-run: emu 204 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 205 206# vcs simulation 207simv: sim-verilog 208 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 209 210simv-run: 211 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 212 213# palladium simulation 214pldm-build: sim-verilog 215 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 216 217pldm-run: 218 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 219 220pldm-debug: 221 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 222 223include Makefile.test 224 225include src/main/scala/device/standalone/standalone_device.mk 226 227.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 228