1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21TOP = $(XSTOP_PREFIX)XSTop 22SIM_TOP = SimTop 23 24FPGATOP = top.TopMain 25SIMTOP = top.SimTop 26 27RTL_SUFFIX ?= sv 28TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 29SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 30 31SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 32TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 33 34MEM_GEN = ./scripts/vlsi_mem_gen 35MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 36 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39ISSUE ?= E.b 40CHISEL_TARGET ?= systemverilog 41 42SUPPORT_CHI_ISSUE = B C E.b 43ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 44$(error "Unsupported CHI issue: $(ISSUE)") 45endif 46 47ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 48$(error At most one target can be specified) 49endif 50 51ifeq ($(MAKECMDGOALS),) 52GOALS = verilog 53else 54GOALS = $(MAKECMDGOALS) 55endif 56 57# JVM memory configurations 58JVM_XMX ?= 40G 59JVM_XSS ?= 256m 60 61# mill arguments for build.sc 62MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 63 64# common chisel args 65FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 66SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 67MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 68 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 69 70# prefix of XSTop or XSNoCTop 71ifneq ($(XSTOP_PREFIX),) 72COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 73endif 74 75# IMSIC use TileLink rather than AXI4Lite 76ifeq ($(IMSIC_USE_TL),1) 77COMMON_EXTRA_ARGS += --imsic-use-tl 78endif 79 80# enable or disable dfx manually 81ifeq ($(DFX),1) 82COMMON_EXTRA_ARGS += --dfx true 83else 84ifeq ($(DFX),0) 85COMMON_EXTRA_ARGS += --dfx false 86endif 87endif 88 89# L2 cache size in KB 90ifneq ($(L2_CACHE_SIZE),) 91COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 92endif 93 94# L3 cache size in KB 95ifneq ($(L3_CACHE_SIZE),) 96COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 97endif 98 99# seperate bus for DebugModule 100ifeq ($(SEPERATE_DM_BUS),1) 101COMMON_EXTRA_ARGS += --seperate-dm-bus 102endif 103 104# configuration from yaml file 105ifneq ($(YAML_CONFIG),) 106COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 107endif 108 109# hart id bits 110ifneq ($(HART_ID_BITS),) 111COMMON_EXTRA_ARGS += --hartidbits $(HART_ID_BITS) 112endif 113 114# public args sumup 115RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 116DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 117override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 118 119# co-simulation with DRAMsim3 120ifeq ($(WITH_DRAMSIM3),1) 121ifndef DRAMSIM3_HOME 122$(error DRAMSIM3_HOME is not set) 123endif 124override SIM_ARGS += --with-dramsim3 125endif 126 127# run emu with chisel-db 128ifeq ($(WITH_CHISELDB),1) 129override SIM_ARGS += --with-chiseldb 130endif 131 132# run emu with chisel-db 133ifeq ($(WITH_ROLLINGDB),1) 134override SIM_ARGS += --with-rollingdb 135endif 136 137# enable ResetGen 138ifeq ($(WITH_RESETGEN),1) 139override SIM_ARGS += --reset-gen 140endif 141 142# run with disable all perf 143ifeq ($(DISABLE_PERF),1) 144override SIM_ARGS += --disable-perf 145endif 146 147# run with disable all db 148ifeq ($(DISABLE_ALWAYSDB),1) 149override SIM_ARGS += --disable-alwaysdb 150endif 151 152# dynamic switch CONSTANTIN 153ifeq ($(WITH_CONSTANTIN),1) 154override SIM_ARGS += --with-constantin 155endif 156 157# emu for the release version 158RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 159DEBUG_ARGS += --enable-difftest 160override PLDM_ARGS += --enable-difftest 161ifeq ($(RELEASE),1) 162override SIM_ARGS += $(RELEASE_ARGS) 163else ifeq ($(PLDM),1) 164override SIM_ARGS += $(PLDM_ARGS) 165else 166override SIM_ARGS += $(DEBUG_ARGS) 167endif 168 169# use RELEASE_ARGS for TopMain by default 170ifeq ($(PLDM), 1) 171TOPMAIN_ARGS += $(PLDM_ARGS) 172else 173TOPMAIN_ARGS += $(RELEASE_ARGS) 174endif 175 176TIMELOG = $(BUILD_DIR)/time.log 177TIME_CMD = time -avp -o $(TIMELOG) 178 179ifeq ($(PLDM),1) 180SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 181SED_ENDIF = `endif // not def SYNTHESIS 182endif 183 184.DEFAULT_GOAL = verilog 185 186help: 187 mill -i xiangshan.runMain $(FPGATOP) --help 188 189version: 190 mill -i xiangshan.runMain $(FPGATOP) --version 191 192jar: 193 mill -i xiangshan.assembly 194 195test-jar: 196 mill -i xiangshan.test.assembly 197 198comp: 199 mill -i xiangshan.compile 200 mill -i xiangshan.test.compile 201 202$(TOP_V): $(SCALA_FILE) 203 mkdir -p $(@D) 204 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 205 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 206 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 207ifeq ($(CHISEL_TARGET),systemverilog) 208 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 209 @git log -n 1 >> .__head__ 210 @git diff >> .__diff__ 211 @sed -i 's/^/\/\// ' .__head__ 212 @sed -i 's/^/\/\//' .__diff__ 213 @cat .__head__ .__diff__ $@ > .__out__ 214 @mv .__out__ $@ 215 @rm .__head__ .__diff__ 216endif 217 218verilog: $(TOP_V) 219 220$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 221 mkdir -p $(@D) 222 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 223 @date -R | tee -a $(TIMELOG) 224 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 225 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 226 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 227ifeq ($(CHISEL_TARGET),systemverilog) 228 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 229 @git log -n 1 >> .__head__ 230 @git diff >> .__diff__ 231 @sed -i 's/^/\/\// ' .__head__ 232 @sed -i 's/^/\/\//' .__diff__ 233 @cat .__head__ .__diff__ $@ > .__out__ 234 @mv .__out__ $@ 235 @rm .__head__ .__diff__ 236ifeq ($(PLDM),1) 237 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 238 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 239else 240ifeq ($(ENABLE_XPROP),1) 241 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 242else 243 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 244endif 245endif 246 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 247endif 248 249sim-verilog: $(SIM_TOP_V) 250 251clean: 252 $(MAKE) -C ./difftest clean 253 rm -rf $(BUILD_DIR) 254 255init: 256 git submodule update --init 257 cd rocket-chip && git submodule update --init cde hardfloat 258 cd openLLC && git submodule update --init openNCB 259 260bump: 261 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 262 263bsp: 264 mill -i mill.bsp.BSP/install 265 266idea: 267 mill -i mill.idea.GenIdea/idea 268 269check-format: 270 mill xiangshan.checkFormat 271 272reformat: 273 mill xiangshan.reformat 274 275# verilator simulation 276emu: sim-verilog 277 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 278 279emu-run: emu 280 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 281 282# vcs simulation 283simv: sim-verilog 284 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 285 286simv-run: 287 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 288 289# palladium simulation 290pldm-build: sim-verilog 291 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 292 293pldm-run: 294 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 295 296pldm-debug: 297 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 298 299include Makefile.test 300 301include src/main/scala/device/standalone/standalone_device.mk 302 303.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 304