1#*************************************************************************************** 2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3# Copyright (c) 2020-2021 Peng Cheng Laboratory 4# 5# XiangShan is licensed under Mulan PSL v2. 6# You can use this software according to the terms and conditions of the Mulan PSL v2. 7# You may obtain a copy of Mulan PSL v2 at: 8# http://license.coscl.org.cn/MulanPSL2 9# 10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13# 14# See the Mulan PSL v2 for more details. 15#*************************************************************************************** 16 17BUILD_DIR = ./build 18RTL_DIR = $(BUILD_DIR)/rtl 19 20TOP = XSTop 21SIM_TOP = SimTop 22 23FPGATOP = top.TopMain 24SIMTOP = top.SimTop 25 26TOP_V = $(RTL_DIR)/$(TOP).v 27SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).v 28 29SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 30TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 31 32MEM_GEN = ./scripts/vlsi_mem_gen 33MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 34SPLIT_VERILOG = ./scripts/split_verilog.sh 35 36IMAGE ?= temp 37CONFIG ?= DefaultConfig 38NUM_CORES ?= 1 39MFC ?= 1 40 41 42ifeq ($(MAKECMDGOALS),) 43GOALS = verilog 44else 45GOALS = $(MAKECMDGOALS) 46endif 47 48# common chisel args 49ifeq ($(MFC),1) 50CHISEL_VERSION = chisel 51FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf" 52SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf" 53MFC_ARGS = --dump-fir --target verilog \ 54 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 55RELEASE_ARGS += $(MFC_ARGS) 56DEBUG_ARGS += $(MFC_ARGS) 57PLDM_ARGS += $(MFC_ARGS) 58else 59CHISEL_VERSION = chisel3 60FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 61SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full 62endif 63 64ifneq ($(XSTOP_PREFIX),) 65RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX) 66DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX) 67PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX) 68endif 69 70# co-simulation with DRAMsim3 71ifeq ($(WITH_DRAMSIM3),1) 72ifndef DRAMSIM3_HOME 73$(error DRAMSIM3_HOME is not set) 74endif 75override SIM_ARGS += --with-dramsim3 76endif 77 78# run emu with chisel-db 79ifeq ($(WITH_CHISELDB),1) 80override SIM_ARGS += --with-chiseldb 81endif 82 83# run emu with chisel-db 84ifeq ($(WITH_ROLLINGDB),1) 85override SIM_ARGS += --with-rollingdb 86endif 87 88# enable ResetGen 89ifeq ($(WITH_RESETGEN),1) 90override SIM_ARGS += --reset-gen 91endif 92 93# run with disable all perf 94ifeq ($(DISABLE_PERF),1) 95override SIM_ARGS += --disable-perf 96endif 97 98# run with disable all db 99ifeq ($(DISABLE_ALWAYSDB),1) 100override SIM_ARGS += --disable-alwaysdb 101endif 102 103# dynamic switch CONSTANTIN 104ifeq ($(WITH_CONSTANTIN),1) 105override SIM_ARGS += --with-constantin 106endif 107 108# emu for the release version 109RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen 110DEBUG_ARGS += --enable-difftest 111PLDM_ARGS += --fpga-platform --enable-difftest 112ifeq ($(GOALS),verilog) 113RELEASE_ARGS += --disable-always-basic-diff 114endif 115ifeq ($(RELEASE),1) 116override SIM_ARGS += $(RELEASE_ARGS) 117else ifeq ($(PLDM),1) 118override SIM_ARGS += $(PLDM_ARGS) 119else 120override SIM_ARGS += $(DEBUG_ARGS) 121endif 122 123TIMELOG = $(BUILD_DIR)/time.log 124TIME_CMD = time -avp -o $(TIMELOG) 125 126SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' 127 128ifeq ($(PLDM),1) 129SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 130SED_ENDIF = `endif // not def SYNTHESIS 131endif 132 133.DEFAULT_GOAL = verilog 134 135help: 136 mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help 137 138$(TOP_V): $(SCALA_FILE) 139 mkdir -p $(@D) 140 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \ 141 --target-dir $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \ 142 --num-cores $(NUM_CORES) $(RELEASE_ARGS) 143ifeq ($(MFC),1) 144 $(SPLIT_VERILOG) $(RTL_DIR) $(TOP).v 145 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(RTL_DIR)" 146endif 147 $(SED_CMD) $@ 148 @git log -n 1 >> .__head__ 149 @git diff >> .__diff__ 150 @sed -i 's/^/\/\// ' .__head__ 151 @sed -i 's/^/\/\//' .__diff__ 152 @cat .__head__ .__diff__ $@ > .__out__ 153 @mv .__out__ $@ 154 @rm .__head__ .__diff__ 155 156verilog: $(TOP_V) 157 158$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 159 mkdir -p $(@D) 160 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 161 @date -R | tee -a $(TIMELOG) 162 $(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \ 163 --target-dir $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \ 164 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 165ifeq ($(MFC),1) 166 $(SPLIT_VERILOG) $(RTL_DIR) $(SIM_TOP).v 167 $(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(RTL_DIR)" 168endif 169 $(SED_CMD) $@ 170 @git log -n 1 >> .__head__ 171 @git diff >> .__diff__ 172 @sed -i 's/^/\/\// ' .__head__ 173 @sed -i 's/^/\/\//' .__diff__ 174 @cat .__head__ .__diff__ $@ > .__out__ 175 @mv .__out__ $@ 176 @rm .__head__ .__diff__ 177ifeq ($(PLDM),1) 178 sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V) 179 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(SIM_TOP_V) 180else 181ifeq ($(ENABLE_XPROP),1) 182 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(SIM_TOP_V) 183else 184 sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V) 185endif 186endif 187ifeq ($(MFC),1) 188 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V) 189endif 190 191sim-verilog: $(SIM_TOP_V) 192 193clean: 194 $(MAKE) -C ./difftest clean 195 rm -rf $(BUILD_DIR) 196 197init: 198 git submodule update --init 199 cd rocket-chip && git submodule update --init cde hardfloat 200 201bump: 202 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 203 204bsp: 205 mill -i mill.bsp.BSP/install 206 207idea: 208 mill -i mill.scalalib.GenIdea/idea 209 210# verilator simulation 211emu: sim-verilog 212 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 213 214emu-run: emu 215 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 216 217# vcs simulation 218simv: sim-verilog 219 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 220 221simv-run: 222 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 223 224# palladium simulation 225pldm-build: sim-verilog 226 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 227 228pldm-run: 229 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 230 231pldm-debug: 232 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) 233 234include Makefile.test 235 236.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 237