xref: /XiangShan/Makefile (revision 7a2fc509e2d355879c4db3dc3f17a6ccacd3d09e) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17TOP = XSTop
18FPGATOP = top.TopMain
19BUILD_DIR = ./build
20TOP_V = $(BUILD_DIR)/$(TOP).v
21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
22TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
23MEM_GEN = ./scripts/vlsi_mem_gen
24
25SIMTOP  = top.SimTop
26IMAGE  ?= temp
27CONFIG ?= DefaultConfig
28NUM_CORES ?= 1
29MFC ?= 0
30
31FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
32SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
33
34# select firrtl compiler
35ifeq ($(MFC),1)
36override FC_ARGS = --mfc
37override FPGA_MEM_ARGS =
38override SIM_MEM_ARGS =
39endif
40
41
42# co-simulation with DRAMsim3
43ifeq ($(WITH_DRAMSIM3),1)
44ifndef DRAMSIM3_HOME
45$(error DRAMSIM3_HOME is not set)
46endif
47override SIM_ARGS += --with-dramsim3
48endif
49
50# emu for the release version
51RELEASE_ARGS = --disable-all --remove-assert --fpga-platform
52DEBUG_ARGS   = --enable-difftest
53ifeq ($(RELEASE),1)
54override SIM_ARGS += $(RELEASE_ARGS)
55else
56override SIM_ARGS += $(DEBUG_ARGS)
57endif
58
59TIMELOG = $(BUILD_DIR)/time.log
60TIME_CMD = time -a -o $(TIMELOG)
61
62SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
63
64# add comments to 'firrtl_black_box_resource_files'
65AWK_CMD = gawk -i inplace 'BEGIN{f=0} /FILE "firrtl_black_box_resource_files.f"/{f=1} !f{print $$0} f{print "//", $$0}'
66
67
68.DEFAULT_GOAL = verilog
69
70help:
71	mill -i XiangShan.runMain $(FPGATOP) --help
72
73$(TOP_V): $(SCALA_FILE)
74	mkdir -p $(@D)
75	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)  \
76		--config $(CONFIG)                                        \
77		$(FPGA_MEM_ARGS)                                          \
78		--num-cores $(NUM_CORES)                                  \
79		$(RELEASE_ARGS) $(FC_ARGS)
80	$(SED_CMD) $@
81ifeq ($(MFC),1)
82	$(AWK_CMD) $@
83endif
84	@git log -n 1 >> .__head__
85	@git diff >> .__diff__
86	@sed -i 's/^/\/\// ' .__head__
87	@sed -i 's/^/\/\//' .__diff__
88	@cat .__head__ .__diff__ $@ > .__out__
89	@mv .__out__ $@
90	@rm .__head__ .__diff__
91
92verilog: $(TOP_V)
93
94SIM_TOP   = SimTop
95SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
96$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
97	mkdir -p $(@D)
98	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
99	@date -R | tee -a $(TIMELOG)
100	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)  \
101		--config $(CONFIG)                                            \
102		$(SIM_MEM_ARGS)                                               \
103		--num-cores $(NUM_CORES)                                      \
104		$(SIM_ARGS) $(FC_ARGS)
105	$(SED_CMD) $@
106ifeq ($(MFC),1)
107	$(AWK_CMD) $@
108endif
109	@git log -n 1 >> .__head__
110	@git diff >> .__diff__
111	@sed -i 's/^/\/\// ' .__head__
112	@sed -i 's/^/\/\//' .__diff__
113	@cat .__head__ .__diff__ $@ > .__out__
114	@mv .__out__ $@
115	@rm .__head__ .__diff__
116	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
117
118sim-verilog: $(SIM_TOP_V)
119
120clean:
121	$(MAKE) -C ./difftest clean
122	rm -rf ./build
123
124init:
125	git submodule update --init
126	cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
127
128bump:
129	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
130
131bsp:
132	mill -i mill.bsp.BSP/install
133
134idea:
135	mill -i mill.scalalib.GenIdea/idea
136
137# verilator simulation
138emu:
139	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
140
141emu-run:
142	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
143
144# vcs simulation
145simv:
146	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
147
148.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
149